N25Q128A11B1241F Numonyx - A DIVISION OF MICRON SEMICONDUCTOR PRODUCTS, INC., N25Q128A11B1241F Datasheet - Page 34
N25Q128A11B1241F
Manufacturer Part Number
N25Q128A11B1241F
Description
IC SRL FLASH 128MB NMX 24-BGAS
Manufacturer
Numonyx - A DIVISION OF MICRON SEMICONDUCTOR PRODUCTS, INC.
Series
Forté™r
Datasheet
1.N25Q128A11B1241F.pdf
(185 pages)
Specifications of N25Q128A11B1241F
Format - Memory
FLASH
Memory Type
FLASH
Memory Size
128M (16M x 8)
Speed
108MHz
Interface
SPI, 3-Wire Serial
Voltage - Supply
1.7 V ~ 2 V
Operating Temperature
-40°C ~ 85°C
Package / Case
24-TBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
N25Q128A11B1241F
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
N25Q128A11B1241F
Manufacturer:
Micron Technology Inc
Quantity:
10 000
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6.1
6.1.1
6.1.2
6.1.3
6.1.4
34/185
Legacy SPI Status Register
The Status Register contains a number of status and control bits that can be read or set by
specific instructions: Read Status Register (RDSR) and Write Status Register (WRSR). This
is available in all the 3 protocols (Extended SPI, DIO-SPI, and QIO-SPI).
Table 3.
WIP bit
The Write In Progress (WIP) bit set to 1 indicates that the memory is busy with a Write
Status Register, Program or Erase cycle. 0 indicates no cycle is in progress.
WEL bit
The Write Enable Latch (WEL) bit set to 1 indicates that the internal Write Enable Latch is
set. When set to 0 the internal Write Enable Latch is reset and no Write Status Register,
Program or Erase instruction is accepted.
BP3, BP2, BP1, BP0 bits
The Block Protect (BP3, BP2, BP1, BP0) bits are non-volatile. They define the size of the
area to be software protected against Program and Erase instructions. These bits are
written with the Write Status Register (WRSR) instruction. When one or more of the Block
Protect (BP3, BP2, BP1, BP0) bits is set to 1, the relevant memory area, as defined in
10.: Protected area sizes (TB bit = 0)
becomes protected against all program and erase instructions. The Block Protect (BP3,
BP2, BP1, BP0) bits can be written provided that the Hardware Protected mode has not
been set. The Bulk Erase (BE) instruction is executed if, and only if, all Block Protect (BP3,
BP2, BP1, BP0) bits are 0.
TB bit
The Top/Bottom (TB) bit is non-volatile. It can be set and reset with the Write Status Register
(WRSR) instruction provided that the Write Enable (WREN) instruction has been issued.
Status register write protect
SRWD
b7
Status register format
BP3
Top/bottom bit
TB
and
Table 11.: Protected area sizes (TB bit =
BP2
Block protect bits
BP1
Write enable latch bit
BP0
WEL
Write in progress bit
1),
WIP
b0
Table
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