N25Q128A11B1241F Numonyx - A DIVISION OF MICRON SEMICONDUCTOR PRODUCTS, INC., N25Q128A11B1241F Datasheet - Page 133
N25Q128A11B1241F
Manufacturer Part Number
N25Q128A11B1241F
Description
IC SRL FLASH 128MB NMX 24-BGAS
Manufacturer
Numonyx - A DIVISION OF MICRON SEMICONDUCTOR PRODUCTS, INC.
Series
Forté™r
Datasheet
1.N25Q128A11B1241F.pdf
(185 pages)
Specifications of N25Q128A11B1241F
Format - Memory
FLASH
Memory Type
FLASH
Memory Size
128M (16M x 8)
Speed
108MHz
Interface
SPI, 3-Wire Serial
Voltage - Supply
1.7 V ~ 2 V
Operating Temperature
-40°C ~ 85°C
Package / Case
24-TBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
N25Q128A11B1241F
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
N25Q128A11B1241F
Manufacturer:
Micron Technology Inc
Quantity:
10 000
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Table 24.
MIORDID
QCFR
ROTP
WREN
WRDI
QCPP
POTP
SSE
SE
BE
PER
PES
RDSR
WRSR
RDLR
WRLR
RFSR
CLFSR
RDNVCR
Instruction
(2)
All attempts to access the memory array during a Write Status Register cycle, a Write Non
Volatile Configuration Register, a Program cycle or an Erase cycle are ignored, and the
internal Write Status Register cycle, Write Non Volatile Configuration Register, Program
cycle or Erase cycle continues unaffected, the only exception is the Program/Erase
Suspend instruction (PES), that can be used to pause all the program and the erase cycles
but the Program OTP (POT), Bulk Erase (BE) and Write Non Volatile Configuration Register.
The suspended program or erase cycle can be resumed by mean of the Program/Erase
Resume instruction (PER). During the program/erase cycles also the polling instructions (to
check if the internal modify cycle is finished by mean of the WIP bit of the Status Register or
of the Program/Erase controller bit of the Flag Status register) are also accepted to allow the
application checking the end of the internal modify cycles, of course these polling
instructions don't affect the internal cycles performing.
Instruction set: QIO-SPI protocol (page 1 of 2)
Multiple I/O read identification
Quad Command Fast Read
Read OTP (Read of OTP area)
Write Enable
Write Disable
Quad Command Page Program
Program OTP (Program of OTP
area)
SubSector Erase
Sector Erase
Bulk Erase
Program/Erase Resume
Program/Erase Suspend
Read Status Register
Write Status Register
Read Lock Register
Write to Lock Register
Read Flag Status Register
Clear Flag Status Register
Read NV Configuration Register
Description
0100 1011
0010 0000
1101 1000
0111 0101
0000 0101
0000 0001
0101 0000
1010 1111
0000 1011
0110 1011
1110 1011
0000 0110
0000 0100
0000 0010
0011 0010
0001 0010
0100 0010
1100 0111
0111 1010
1110 1000
1110 0101
0111 0000
1011 0101
Code (BIN)
Instruction
One-byte
AFh
0Bh
6Bh
EBh
4Bh
06h
04h
02h
32h
12h
42h
20h
D8h
C7h
7Ah
75h
05h
01h
E8h
E5h
50h
B5h
70h
Instruction
One-byte
(HEX)
Code
0
3
3
3
3
0
0
3
3
3
3
3
3
0
0
0
0
0
3
3
0
0
0
Address
bytes
0
10
10
10
10
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Dummy
clock
cycle
(1)
(1)
(1)
(1)
1 to 3
1 to
1 to
1 to
1 to 65
0
0
1 to 256
1 to 256
1 to 256
1 to 65
0
0
0
0
0
1 to
1
1 to
1
1 to
0
2
bytes
Data
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