PI7C8154BNAE Pericom Semiconductor, PI7C8154BNAE Datasheet - Page 73

• Manufacturer Part Number: PI7C8154BNAE
• Description: IC PCI-PCI BRIDGE ASYNC 304-PBGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8154BNAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 304-BGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12
P_M66EN is HIGH and S_M66EN is LOW, the S_CLKOUT[9:0] outputs will be equal to half of
the ASYN_CLKIN. The PI7C8154B in asynchronous mode may run in the following frequencies:
Table 11-1 VALID ASYNCHRONOUS CLOCK FREQUENCIES
PCI POWER MANAGEMENT
PI7C8154B incorporates functionality that meets the requirements of the PCI Power Management
Specification, Revision 1.0. These features include:
Table 12-1 shows the states and related actions that the bridge performs during power management
transitions. (No other transactions are permitted.)
Table 12-1 POWER MANAGEMENT TRANSITIONS
PME# signals are routed from downstream devices around PCI-to-PCI bridges. PME# signals do
not pass through PCI-to-PCI bridges.
D0
D0
D0
D0
D3
D3
D3
Current Status
HOT
COLD
COLD
PCI Power Management registers using the Enhanced Capabilities Port (ECP) address
mechanism
Support for D0, D3
Support for D0, D1, D2, D3
bridge
Support of the B2 secondary bus power state when in the D3
25MHz to 66MHz
Primary (MHz)
D3
D3
D2
D1
D0
D3
D0
COLD
HOT
COLD
Next State
HOT
and D3
HOT
COLD
Page 73 of 114
, and D3
Power has been removed from PI7C8154B. A power-up reset must be
performed to bring PI7C8154B to D0.
If enabled to do so by the BPCCE pin, PI7C8154B will disable the
secondary clocks and drive them LOW.
Unimplemented. PI7C8154B will ignore the write to the power state bits.
Power state will remain at D0.
Unimplemented. PI7C8154B will ignore the write to the power state bits.
Power state will remain at D0.
PI7C8154B enables secondary clock outputs and performs an internal
chip reset. Signal S_RST# will not be asserted. All registers will be
returned to the reset values and buffers will be cleared.
Power has been removed from PI7C8154B. A power-up reset must be
performed to bring PI7C8154B to D0.
Power-up reset. PI7C8154B performs the standard power-up reset
functions as described in Section 11.
power management states
COLD
power management states for devices behind the
*Up to 80MHz on the PI7C8154B-80 only
Action
HOT
25MHz to 66MHz*
Secondary (MHz)
ASYNCHRONOUS 2-PORT
power management state
JUNE 2008 REVISION 1.1
PCI-to-PCI BRIDGE
Advance Information
PI7C8154B