PI7C8154BNAE Pericom Semiconductor, PI7C8154BNAE Datasheet - Page 23

• Manufacturer Part Number: PI7C8154BNAE
• Description: IC PCI-PCI BRIDGE ASYNC 304-PBGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8154BNAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 304-BGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2
2.1
SIGNAL DEFINITIONS
This Chapter offers information about PCI transactions, transaction forwarding across PI7C8154B,
and transaction termination. The PI7C8154B has two 128-byte buffers for read data buffering of
upstream and downstream transactions. Also, PI7C8154B has two 128-byte buffers for write data
buffering of upstream and downstream transactions.
TYPES OF TRANSACTIONS
This section provides a summary of PCI transactions performed by PI7C8154B. Table 2-1 lists the
command code and name of each PCI transaction. The Master and Target columns indicate support
for each transaction when PI7C8154B initiates transactions as a master, on the primary and
secondary buses, and when PI7C8154B responds to transactions as a target, on the primary and
secondary buses.
Table 2-1 PCI TRANSACTIONS
As indicated in Table 2-1, the following PCI commands are not supported by PI7C8154B:
Types of Transactions
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
LOCATION
PI7C8154B never initiates a PCI transaction with a reserved command code and, as a target,
PI7C8154B ignores reserved command codes.
PI7C8154B does not generate interrupt acknowledge transactions. PI7C8154B ignores
interrupt acknowledge transactions as a target.
PI7C8154B does not respond to special cycle transactions. PI7C8154B cannot guarantee
delivery of a special cycle transaction to downstream buses because of the broadcast nature of
the special cycle command and the inability to control the transaction as a target. To generate
BALL
AC19
AC21
AC23
Interrupt Acknowledge
Special Cycle
I/O Read
I/O Write
Reserved
Reserved
Memory Read
Memory Write
Reserved
Reserved
Configuration Read
Configuration Write
Memory Read Multiple
Dual Address Cycle
Memory Read Line
Memory Write and Invalidate
PIN NAME
P_AD[55]
P_AD[49]
VSS
Page 23 of 112
TYPE
TS
TS
P
Initiates as Master
Primary
N
Y
Y
Y
N
N
Y
Y
N
N
N
Y (Type 1 only)
Y
Y
Y
Y
LOCATION
BALL
AC20
AC22
-
Secondary
N
Y
Y
Y
N
N
Y
Y
N
N
Y
Y
Y
Y
Y
Y
VSS
-
PIN NAME
EE_EN#
ASYNCHRONOUS 2-PORT
JUNE 2008 REVISION 1.1
Responds as Target
N
N
Y
Y
N
N
Y
Y
N
N
Y
Y
Y
Y
Y
Primary
Y
PCI-to-PCI BRIDGE
Advance Information
Secondary
N
N
Y
Y
N
N
Y
Y
N
N
N
Y (Type 1 only)
Y
Y
Y
Y
TYPE
PI7C8154B
P
I
-