PI7C8154BNAE Pericom Semiconductor, PI7C8154BNAE Datasheet - Page 28

• Manufacturer Part Number: PI7C8154BNAE
• Description: IC PCI-PCI BRIDGE ASYNC 304-PBGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8154BNAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 304-BGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.6.6
2.7
2.7.1
2.7.2
Delayed write transactions are accepted as long as at least one open entry in the delayed transaction
queue exists. Therefore, several posted and delayed write transactions can exist in data buffers at
the same time. See Chapter 4 for information about how multiple posted and delayed write
transactions are ordered.
FAST BACK-TO-BACK TRANSACTIONS
PI7C8154B is capable of decoding and forwarding fast back-to-back write transactions. When
PI7C8154B cannot accept the second transaction because of buffer space limitations, it returns a
target retry to the initiator. The fast back-to-back enable bit must be set in the command register for
upstream write transactions, and in the bridge control register for downstream write transactions.
READ TRANSACTIONS
Delayed read forwarding is used for all read transactions crossing PI7C8154B. Delayed read
transactions are treated as either prefetchable or non-prefetchable. Table 2-5 shows the read
behavior, prefetchable or non-prefetchable, for each type of read operation.
PREFETCHABLE READ TRANSACTIONS
A prefetchable read transaction is a read transaction where PI7C8154B performs speculative
DWORD reads, transferring data from the target before it is requested from the initiator. This
behavior allows a prefetchable read transaction to consist of multiple data transfers. However, byte
enable bits cannot be forwarded for all data phases as is done for the single data phase of the non-
prefetchable read transaction. For prefetchable read transactions, PI7C8154B forces all byte enable
bits to be on for all data phases.
Prefetchable behavior is used for memory read line and memory read multiple transactions, as well
as for memory read transactions that fall into prefetchable memory space.
The amount of data that is prefetched depends on the type of transaction. The amount of
prefetching may also be affected by the amount of free buffer space available in PI7C8154B, and
by any read address boundaries encountered.
Prefetching should not be used for those read transactions that have side effects in the target device,
that is, control and status registers, FIFO’s, and so on. The target device’s base address register or
registers indicate if a memory address region is prefetchable.
NON-PREFETCHABLE READ TRANSACTIONS
A non-prefetchable read transaction is a read transaction where PI7C8154B requests one and only
one DWORD from the target and disconnects the initiator after delivery of the first DWORD of
read data. Unlike prefetchable read transactions, PI7C8154B forwards the read byte enable
information for the data phase.
Non-prefetchable behavior is used for I/O and configuration read transactions, as well as for
memory read transactions that fall into non-prefetchable memory space.
Page 28 of 112
ASYNCHRONOUS 2-PORT
JUNE 2008 REVISION 1.1
PCI-to-PCI BRIDGE
Advance Information
PI7C8154B