PI7C9X20508GPBNDE Pericom Semiconductor, PI7C9X20508GPBNDE Datasheet

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PI7C9X20508GP PCI EXPRESS PACKET SWITCH DATASHEET REVISION 1.5 June 2009 ST 3545 North 1 Street, San Jose, CA 95134 Telephone: 1-877-PERICOM, (1-877-737-4266) FAX: 408-435-1100 Internet: http://www.pericom.com ...

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... A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system affect its safety or effectiveness. Pericom Semiconductor Corporation reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product ...

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... Modified Chapter 7 Registers (7.2.50 Replay Time-Out Counter, 7.2.52 Switch Operation Mode Bit[14,15,17], 7.2.53 Switch Operation Mode Bit[8:15], 7.2.64 PCI Express Capability Bit[24] , 7.2.70 Link Status Bit[28], 7.2.103 Power Budgeting Data, 7.2.104 Power Budget Capability) June 2009 – Revision 1.5 Pericom Semiconductor 5Port-8Lane PCI Express Switch Page PI7C9X20508GP TM ...

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... Updated Chapter 3.3 Hot Plug Signals (PWR_IND, ATT_IND) Updated Chapter 3.4 Miscellaneous Signals (PWR_SAV pin removed, EEPD) Updated Chapter 3.5 JTAG Boundary Scan Signals (TMS, TDI, TRST_L) June 2009 – Revision 1.5 Pericom Semiconductor 5Port-8Lane PCI Express Switch Page PI7C9X20508GP TM GreenPacket ...

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... DEVICE ID REGISTER – OFFSET 00h.............................................................................................35 7.2.3 COMMAND REGISTER – OFFSET 04h............................................................................................35 7.2.4 PRIMARY STATUS REGISTER – OFFSET 04h.................................................................................36 7.2.5 REVISION ID REGISTER – OFFSET 08h .........................................................................................36 June 2009 – Revision 1.5 Pericom Semiconductor 5Port-8Lane PCI Express Switch Page PI7C9X20508GP TM GreenPacket Family Datasheet ...

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... NEXT ITEM POINTER REGISTER – OFFSET B8h ..........................................................................48 7.2.56 SUBSYSTEM VENDOR ID REGISTER – OFFSET BCh....................................................................49 7.2.57 SUBSYSTEM ID REGISTER – OFFSET BCh ....................................................................................49 7.2.58 GPIO CONTROL REGISTER – OFFSET D8h (Upstream Port Only)...............................................49 June 2009 – Revision 1.5 Pericom Semiconductor 5Port-8Lane PCI Express Switch Page PI7C9X20508GP TM GreenPacket Family Datasheet ...

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... POWER BUDGETING DATA REGISTER – OFFSET 214h ..........................................................69 7.2.104 POWER BUDGET CAPABILITY REGISTER – OFFSET 218h .....................................................69 8 CLOCK SCHEME ........................................................................................................................................................70 9 HOT PLUG OPERATION ...........................................................................................................................................71 10 IEEE 1149.1 COMPATIBLE JTAG CONTROLLER...............................................................................................72 10.1 INSTRUCTION REGISTER ......................................................................................................................72 June 2009 – Revision 1.5 Pericom Semiconductor 5Port-8Lane PCI Express Switch Page PI7C9X20508GP TM GreenPacket Family Datasheet ...

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... JTAG BOUNDARY SCAN REGISTER ORDER......................................................................................73 11 POWER MANAGEMENT ...........................................................................................................................................75 12 ELECTRICAL AND TIMING SPECIFICATIONS ..................................................................................................76 12.1 ABSOLUTE MAXIMUM RATINGS ........................................................................................................76 12.2 DC SPECIFICATIONS ..............................................................................................................................76 12.3 AC SPECIFICATIONS ..............................................................................................................................77 13 PACKAGE INFORMATION.......................................................................................................................................79 14 ORDERING INFORMATION.....................................................................................................................................81 June 2009 – Revision 1.5 Pericom Semiconductor 5Port-8Lane PCI Express Switch Page PI7C9X20508GP TM GreenPacket Family Datasheet ...

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... ABLE BOUNDARY SCAR REGISTER DEFINITION T 12-1 A ABLE BSOLUTE MAXIMUM RATINGS T 12-2 DC ABLE ELECTRICAL CHARACTERISTICS T 12 ABLE RANSMITTER HARACTERISTICS T 12 ABLE ECEIVER HARACTERISTICS June 2009 – Revision 1.5 Pericom Semiconductor I PI7C9X20508GP............................................................32 MPLEMENTATION ON ........................................................................................................................79 ................................................................................................................. )............................................................................................18 ALUES NOM N C .............................................................................18 OMINAL URRENT DEQ [3:0]................................................................................................... ..........................................................................................22 RDERING ULES .................................................................................................... ...

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... Programmable driver current and de-emphasis level at each individual port  Low Power Dissipation at 1. normal mode  Industrial Temperature Range -40  256-pin PBGA 17mm x 17mm package, 1.0 mm Ball Pitch June 2009 – Revision 1.5 Pericom Semiconductor and L3 link power states Ready and D3 device power states ...

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... VC1 queues can be reassigned to VC0 and enable each of the ingress ports to handle more data traffic bursts. This virtual channel resource relocation feature enhances the performance of the PCIe Switch further. June 2009 – Revision 1.5 Pericom Semiconductor 5Port-8Lane PCI Express Switch Page PI7C9X20508GP ...

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... NAME PIN VC1_EN F4 SLOT_IMP [4:1] *T6, G4, G2, G1 June 2009 – Revision 1.5 Pericom Semiconductor 5Port-8Lane PCI Express Switch TYPE DESCRIPTION I Reference Clock Input Pairs: Connect to external 100MHz differential clock. The input clock signals must be delivered to the clock buffer cell through an AC-coupled interface so that only the AC information of the clock is received, converted, and buffered ...

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... SMBCLK T4 SMBDATA T5 SCAN_EN N14 June 2009 – Revision 1.5 Pericom Semiconductor 5Port-8Lane PCI Express Switch TYPE DESCRIPTION I Hot Plug Capability: It determines if the downstream port is able to support hot plug capability. HOTPLUG [x] is correspondent to Portx, where x=1,2,3,4. When HOTPLUG [x] is high, Portx supports hot plug operation ...

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... TMS L13 TDO M13 TDI L14 June 2009 – Revision 1.5 Pericom Semiconductor 5Port-8Lane PCI Express Switch TYPE DESCRIPTION O Port PHY Error Status: These pins are used to display the PHY Error status of the ports. When PORTERR is flashing (alternating high and low signals), it indicates that a PHY error is detected When it is low, no PHY error is detected ...

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... K14, L15, L16, M1, M14, N3, N16, P2, P10, R4, R12, T9, T11, T14 June 2009 – Revision 1.5 Pericom Semiconductor 5Port-8Lane PCI Express Switch Type Description I Test Reset (Active LOW): Active LOW signal to reset the TAP controller into an initialized state. The pin has internal pull-up. When JTAG boundary scan function is not implemented, this pin should be pulled low through a 5 ...

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... C15 VSS G15 C16 VSS G16 D1 VSS H1 D2 VSS H2 D3 VDDCAUX H3 D4 TEST2 H4 D5 DWNRST_L[3] H5 June 2009 – Revision 1.5 Pericom Semiconductor 5Port-8Lane PCI Express Switch NAME PIN NAME PERP[3] J1 SLOTCLK[2] PERN[3] J2 VSS VDDCAUX J3 SLOTCLK[3] RESET_L J4 VDDR DWNRST_L[4] J5 GPIO[0] DWNRST_L[2] J6 GPIO[1] ...

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... D11 VDDA H11 D12 NC H12 D13 NC H13 D14 VDDR H14 D15 PERN[7] H15 D16 PERP[7] H16 June 2009 – Revision 1.5 Pericom Semiconductor 5Port-8Lane PCI Express Switch NAME PIN NAME VDDC M6 DTX[2] VDDC M7 VDDC VSS M8 ATT_BTN[3] VSS M9 VDDC VSS M10 PWR_ENA_L[4] ...

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... Table 5-2 Ratio of Actual Current and Nominal Current DTX [3:0] ACTUAL CURRENT / NOMINAL CURRENT 0000 0001 0010 0011 0100 0101 1 Multiple lanes could share the PLL. June 2009 – Revision 1.5 Pericom Semiconductor NOMINAL DRIVER CURENT Reserved 1.00 1.05 1.10 1.15 1 ...

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... ISI related jitter. The following table shows a simple guideline for selecting the appropriate value to adapt with different lengths or connector numbers in various applications. Table 5-4 Rx Equalizer Settings (RXEQCTL) RXEQCTL [1] RXEQCTL [ June 2009 – Revision 1.5 Pericom Semiconductor 1.30 1.35 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 – ...

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... If the incoming packet can not be forwarded to any other port due to a miss to hit the defined address range or targeted ID, this is considered as Unsupported Request (UR) packet, which is similar to a master abort event in PCI protocol. June 2009 – Revision 1.5 Pericom Semiconductor 5Port-8Lane PCI Express Switch Page PI7C9X20508GP ...

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... CPLH queue provides TLP header space for completion packets. Each header space takes twelve bytes to accommodate a 3-DW header. Please note that there are no 4-DW completion headers. There are two CPLH queues for VC0 and VC1 respectively. June 2009 – Revision 1.5 Pericom Semiconductor 5Port-8Lane PCI Express Switch Page PI7C9X20508GP ...

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... Completions. Otherwise, deadlocks may occur when some older bridges, which do not support delayed transactions are mixed with PCIe Switch in the same system. A fairness algorithm is used to arbitrate between the Posted Write queue and the Non-posted transaction queue June 2009 – Revision 1.5 Pericom Semiconductor Read Non-posted Write Request ...

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... TLP generated from VC arbiter, respond with the completion packets when the local resource (i.e. configuration register) is accessed, and regenerate the message that terminates at receiver acting as an upstream port. June 2009 – Revision 1.5 Pericom Semiconductor 5Port-8Lane PCI Express Switch Page PI7C9X20508GP ...

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... Max_Payload_Size Support / ASPM Support / Role_Base Error Reporting / RefClk ppm PM Data for Port 0 PM Data for Port 1 PM Data for Port 2 PM Data for Port 3 PM Data for Port 4 June 2009 – Revision 1.5 Pericom Semiconductor 7 – 0 Vendor ID Device ID Subsystem Vender ID Subsystem ID Difference ...

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... Acknowledge Latency Timer for Port 1 Acknowledge Latency Timer for Port 2 Acknowledge Latency Timer for Port 3 Acknowledge Latency Timer for Port 4 June 2009 – Revision 1.5 Pericom Semiconductor 7 – 0 Reserved Slot Clock / LPVC Count / Port Num, Port 0 Slot Implemented / Slot Clock / LPVC Count ...

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... B0h(port 0~4) B0h : Bit [14] B0h(port 0~4) B0h : Bit [15] B4h(port 0~4) B4h : Bit [15] B0h(port 0~4) June 2009 – Revision 1.5 Pericom Semiconductor 7 – 0 PHY Parameter for Port 1 PHY Parameter for Port 2 PHY Parameter for Port 3 PHY Parameter for Port 4 Reserved Reserved Reserved ...

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... Bit [3] 80h (Port 4) 80h: Bit [24:22] 80h: Bit [25] 80h: Bit [26] 80h: Bit [29:28] June 2009 – Revision 1.5 Pericom Semiconductor 5Port-8Lane PCI Express Switch DESCRIPTION  Bit [7] : Disable Power Management Capability RefClk ppm Difference for Port  Bit [9:8]: It represents RefClk ppm difference between the two ends in one link ...

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... Bit [4] ECh (Port 2) ECh: Bit [26:24] 154h (Port 2) 154h: Bit [7:1] June 2009 – Revision 1.5 Pericom Semiconductor 5Port-8Lane PCI Express Switch DESCRIPTION Power Management Data for Port 4  Bit [15:8] – read only as Data register Slot Clock Configuration for Port 0  ...

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... Bit [7:0] 52h 15Ch (Port 1) 15Ch– Bit [22:16] 160h– Bit [7:0] June 2009 – Revision 1.5 Pericom Semiconductor 5Port-8Lane PCI Express Switch DESCRIPTION PCIe Capability Slot Implemented for Port 3  Bit [0]: When set, the slot is implemented for Port 3 Slot Clock Configuration for Port 3  ...

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... B4h (Port 0) B4h: Bit [31:16] 92h B4h (Port 1) B4h: Bit [31:16] June 2009 – Revision 1.5 Pericom Semiconductor 5Port-8Lane PCI Express Switch DESCRIPTION VC1 MAX Time Slot and TC/VC Map for Port 2  Bit [6:0]: The maximum time slot supported by VC1  ...

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... B4h (Port 3) B4h : Bit [14] A8h B4h (Port 4) B4h: Bit [13:8] B4h (Port 4) B4h : Bit [14] June 2009 – Revision 1.5 Pericom Semiconductor 5Port-8Lane PCI Express Switch DESCRIPTION PHY Parameter for Port 2  Bit [31:16]: PHY Parameter PHY Parameter for Port 3  Bit [31:16]: PHY Parameter PHY Parameter for Port 4  ...

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... Table 6-1 SMBus Address Pin Configuration BIT SMBus Address 0 GPIO[5] 1 GPIO[6] 2 GPIO[ June 2009 – Revision 1.5 Pericom Semiconductor 5Port-8Lane PCI Express Switch Processor Other SMBus (SMBus Master) Devices Page PI7C9X20508GP TM GreenPacket Family Datasheet ...

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... Message Control Reserved VPD Register Length in Bytes (14h) ACK Latency Timer Reserved SSID June 2009 – Revision 1.5 Pericom Semiconductor DEFINITION Hardware Initialization Read Only Read / Write Read / Write 1 to Clear Sticky - Read Only / Write 1 to Clear Sticky - Read / Write Sticky – Read Only 23 – ...

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... Port VC Status Register Port Arbitration Table Offset=4 VC Resource Status Register (0) Port Arbitration Table Offset=6 VC Resource Status Register (1) Next Capability Offset=000h June 2009 – Revision 1.5 Pericom Semiconductor 23 – EEPROM Address Next Item Pointer=00 Device Capabilities Device Control Link Capabilities Link Control ...

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... SERR# enable Fast Back-to-Back 9 Enable 10 Interrupt Disable 15:11 Reserved June 2009 – Revision 1.5 Pericom Semiconductor 5Port-8Lane PCI Express Switch TYPE DESCRIPTION RO Identifies Pericom as the vendor of this device. The default value may be changed by SMBus or auto-loading from EEPROM. Reset to 12D8h. TYPE DESCRIPTION RO Identifies this device as the PI7C9X20508GP ...

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... Programming Interface 23:16 Sub-Class Code 31:24 Base Class Code June 2009 – Revision 1.5 Pericom Semiconductor 5Port-8Lane PCI Express Switch TYPE DESCRIPTION RO Reset to 000b. Indicates that an INTx Interrupt Message is pending internally to the device the Switch, the forwarding of INTx messages from the downstream device of the Switch port is not reflected in this bit ...

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... BIT FUNCTION Subordinate Bus 23:16 Number June 2009 – Revision 1.5 Pericom Semiconductor 5Port-8Lane PCI Express Switch TYPE DESCRIPTION The cache line size register is set by the system firmware and the operating system cache line size. This field is implemented by PCI Express devices as a ...

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... Signaled Target 27 Abort Received Target 28 Abort Received Master 29 Abort June 2009 – Revision 1.5 Pericom Semiconductor 5Port-8Lane PCI Express Switch TYPE DESCRIPTION Does not apply to PCI Express. Must be hardwired to 00h. RO TYPE DESCRIPTION RO Read as 01h to indicate 32-bit I/O addressing. Defines the bottom address of the I/O address range for the bridge to determine when to forward I/O transactions from one interface to the other ...

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... PREFETCHABLE MEMORY LIMIT ADDRESS REGISTER – OFFSET 24h BIT FUNCTION 19:16 64-bit addressing June 2009 – Revision 1.5 Pericom Semiconductor 5Port-8Lane PCI Express Switch TYPE DESCRIPTION Reset to 0b. Set to 1 when the switch sends an ERR_FATAL or ERR_NONFATAL Message, and the SERR Enable bit in the Bridge Control register is 1. ...

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... CAPABILITY POINTER REGISTER – OFFSET 34h BIT FUNCTION 7:0 Capability Pointer June 2009 – Revision 1.5 Pericom Semiconductor 5Port-8Lane PCI Express Switch TYPE DESCRIPTION Defines the top address of an address range for the bridge to determine when to forward memory read and write transactions from one interface to the other ...

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... ISA Enable 19 VGA Enable 20 VGA 16-bit decode 21 Master Abort Mode 22 Secondary Bus Reset June 2009 – Revision 1.5 Pericom Semiconductor 5Port-8Lane PCI Express Switch TYPE DESCRIPTION Reset to 80h. TYPE DESCRIPTION RW Reset to 00h. TYPE DESCRIPTION The Switch implements INTA virtual wire interrupt signals to represent hot- plug events at downstream ports ...

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... POWER MANAGEMENT DATA REGISTER – OFFSET 84h BIT FUNCTION 1:0 Power State June 2009 – Revision 1.5 Pericom Semiconductor 5Port-8Lane PCI Express Switch TYPE DESCRIPTION Does not apply to PCI Express. Must be hardwired to 0b. RO Does not apply to PCI Express. Must be hardwired to 0b. ...

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... Capabilities ID 7.2.36 NEXT ITEM POINTER REGISTER – OFFSET 8Ch (Downstream Port Only) BIT FUNCTION 15:8 Next Item Pointer June 2009 – Revision 1.5 Pericom Semiconductor 5Port-8Lane PCI Express Switch TYPE DESCRIPTION 00b: D0 state 01b: D1 state 10b: D2 state 11b: D3 hot state Reset to 00b. ...

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... NEXT ITEM POINTER REGISTER – OFFSET 9Ch (Upstream Port Only) BIT FUNCTION June 2009 – Revision 1.5 Pericom Semiconductor 5Port-8Lane PCI Express Switch TYPE DESCRIPTION 0b: The function is prohibited from using MSI to request service 1b: The function is permitted to use MSI to request service and is prohibited ...

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... FUNCTION 15:8 Next Item Pointer 7.2.47 LENGTH REGISTER – OFFSET A4h BIT FUNCTION 31:16 Length Information June 2009 – Revision 1.5 Pericom Semiconductor 5Port-8Lane PCI Express Switch TYPE DESCRIPTION Pointer points to the Vendor specific capability register (A4h). RO Reset to A4h. TYPE DESCRIPTION RO Reset to 00b ...

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... Timer Enable User ACK 30 Latency 31 Reserved 7.2.52 SWITCH OPERATION MODE – OFFSET B4h (Upstream Port) BIT FUNCTION June 2009 – Revision 1.5 Pericom Semiconductor 5Port-8Lane PCI Express Switch TYPE DESCRIPTION RW Reset to 04001060h. TYPE DESCRIPTION RW Reset to 04000800h. TYPE DESCRIPTION A 12-bit register contains a user-defined value. The default value may be changed by SMBus or auto-loading from EEPROM ...

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... Transmit Equalization Receive Termination 27:26 Adjustment June 2009 – Revision 1.5 Pericom Semiconductor 5Port-8Lane PCI Express Switch TYPE DESCRIPTION When set, a store-forward mode is used. Otherwise, the chip is working under cut-through mode. The default value may be changed by SMBus or auto- RW loading from EEPROM. ...

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... NEXT ITEM POINTER REGISTER – OFFSET B8h BIT FUNCTION 15:8 Next Item Pointer June 2009 – Revision 1.5 Pericom Semiconductor 5Port-8Lane PCI Express Switch TYPE DESCRIPTION It indicates the status of the strapping pins TXTRMADJ[1:0]. The default HwInt value may be changed by SMBus or auto-loading from EEPROM. ...

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... GPIO [3] Input GPIO [3] Output 13 Enable GPIO [3] Output 14 Register 15 Reserved June 2009 – Revision 1.5 Pericom Semiconductor 5Port-8Lane PCI Express Switch TYPE DESCRIPTION RO It indicates the sub-system vendor id. The default value may be changed by SMBus or auto-loading from EEPROM. Reset to 0000h. TYPE DESCRIPTION RO It indicates the sub-system device id. The default value may be changed by SMBus or auto-loading from EEPROM ...

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... EEPROM Start 1 EEPROM Command EEPROM Error 2 Status EEPROM Autoload 3 Success June 2009 – Revision 1.5 Pericom Semiconductor 5Port-8Lane PCI Express Switch TYPE DESCRIPTION RO State of GPIO [4] pin. 0b: GPIO [ input pin 1b: GPIO [ output pin RW Reset to 0b. Value of this bit will be output to GPIO [4] pin if GPIO [4] is configured as an output pin ...

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... PCI EXPRESS CAPABILITIES REGISTER – OFFSET E0h BIT FUNCTION 19:16 Capability Version June 2009 – Revision 1.5 Pericom Semiconductor 5Port-8Lane PCI Express Switch TYPE DESCRIPTION 0b: EEPROM autoload was unsuccessful or is disabled 1b: EEPROM autoload occurred successfully after PREST. Configuration RO registers were loaded with values stored in the EEPROM Reset to 0b ...

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... Limit Value Captured Slot Power 27:26 Limit Scale 31:28 Reserved June 2009 – Revision 1.5 Pericom Semiconductor 5Port-8Lane PCI Express Switch TYPE DESCRIPTION Indicates the type of PCI Express logical device. RO Reset to 0101b (Upstream port). Reset to 0110b (Downstream port). When set, indicates that the PCIe Link associated with this Port is connected to a slot ...

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... Reserved 7.2.67 DEVICE STATUS REGISTER – OFFSET E8h BIT FUNCTION Correctable Error 16 Detected June 2009 – Revision 1.5 Pericom Semiconductor 5Port-8Lane PCI Express Switch TYPE DESCRIPTION 0b: Disable Correctable Error Reporting 1b: Enable Correctable Error Reporting RW Reset to 0b. 0b: Disable Non-Fatal Error Reporting 1b: Enable Non-Fatal Error Reporting RW Reset to 0b ...

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... L0s Exit Latency L1 Exit 17:15 Latency 19:18 Reserved June 2009 – Revision 1.5 Pericom Semiconductor 5Port-8Lane PCI Express Switch TYPE DESCRIPTION Asserted when non-fatal error is detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control RW1C register ...

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... LINK STATUS REGISTER – OFFSET F0h BIT FUNCTION 19:16 Link Speed June 2009 – Revision 1.5 Pericom Semiconductor 5Port-8Lane PCI Express Switch TYPE DESCRIPTION For a Downstream Port, this bit must be set the component supports the optional capability of reporting the DL_Active state of the Data Link Control and Management State Machine ...

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... Power Indicator 4 Present 5 Hot-Plug Surprise 6 Hot-Plug Capable June 2009 – Revision 1.5 Pericom Semiconductor 5Port-8Lane PCI Express Switch TYPE DESCRIPTION Indicates the negotiated width of the given PCIe link. RO Reset to 000100b (x4) for the upstream port. Reset to 000001b (x1) for the downstream port. When set, indicates a Link training error occurred. ...

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... Enable Attention Indicator 7:6 Control June 2009 – Revision 1.5 Pericom Semiconductor 5Port-8Lane PCI Express Switch TYPE DESCRIPTION It applies to Downstream Port only. In combination with the Slot Power Limit Scale value, specifies the upper limit on power supplied by slot. Writes to this register also cause the Port to send the Set_Slot_Power_Limit message. The RW default value may be changed by SMBus or auto-loading from EEPROM ...

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... Presence Detect State 23 Reserved Data Link Layer 24 State Changed 31:25 Reserved June 2009 – Revision 1.5 Pericom Semiconductor 5Port-8Lane PCI Express Switch TYPE DESCRIPTION Controls the display of Power Indicator. 00b: Reserved 01b: On 10b: Blink RW 11b: Off Writes to this register also cause the Port to send the POWER_INDICATOR_* Messages ...

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... Completion Status Receiver Overflow 17 Status Malformed TLP 18 Status June 2009 – Revision 1.5 Pericom Semiconductor 5Port-8Lane PCI Express Switch TYPE DESCRIPTION Read as 0001h to indicate that these are PCI express extended capability RO registers for advance error reporting. TYPE DESCRIPTION Read as 1h. Indicates PCI-SIG defined PCI Express capability structure version number ...

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... ECRC Error Mask Unsupported Request 20 Error Mask 31:21 Reserved June 2009 – Revision 1.5 Pericom Semiconductor 5Port-8Lane PCI Express Switch TYPE DESCRIPTION When set, indicates that an ECRC Error has been detected. RW1CS Reset to 0b. When set, indicates that an Unsupported Request event has occurred. ...

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... Reserved 7.2.80 CORRECTABLE ERROR STATUS REGISTER – OFFSET 110 h BIT FUNCTION 0 Receiver Error Status 5:1 Reserved 6 Bad TLP Status June 2009 – Revision 1.5 Pericom Semiconductor 5Port-8Lane PCI Express Switch TYPE DESCRIPTION 0b: Non-Fatal 1b: Fatal RWS Reset to 1b. RO Reset to 000b. 0b: Non-Fatal 1b: Fatal RWS Reset to 1b ...

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... FUNCTION 4:0 First Error Pointer ECRC Generation 5 Capable June 2009 – Revision 1.5 Pericom Semiconductor 5Port-8Lane PCI Express Switch TYPE DESCRIPTION When set, the event of Bad DLLP has been received is detected. RW1CS Reset to 0b. When set, the REPLAY_NUM Rollover event is detected. ...

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... PORT VC CAPABILITY REGISTER 1 – OFFSET 144h BIT FUNCTION 2:0 Extended VC Count 3 Reserved June 2009 – Revision 1.5 Pericom Semiconductor 5Port-8Lane PCI Express Switch TYPE DESCRIPTION When set, it enables the generation of ECRC when needed. RWS Reset to 0b. When set, it indicates the switch has the capability to check ECRC. ...

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... FUNCTION VC Arbitration Table 16 Status 31:17 Reserved June 2009 – Revision 1.5 Pericom Semiconductor 5Port-8Lane PCI Express Switch TYPE DESCRIPTION It indicates the number of extended Virtual Channels in addition to the default VC belonging to the low-priority VC (LPVC) group. The default value may RO be changed by SMBus or auto-loading from EEPROM. ...

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... VC ID 30:27 Reserved 31 VC Enable June 2009 – Revision 1.5 Pericom Semiconductor 5Port-8Lane PCI Express Switch TYPE DESCRIPTION It indicates the types of Port Arbitration supported by the VC resource. The switch supports Hardware fixed arbitration scheme, e.g., Round Robin, Weight Round Robin (WRR) arbitration with 128 phases (3~4 enabled ports) RO and Time-based WRR with 128 phases (3~4 enabled ports) ...

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... BIT FUNCTION 7:0 TC/VC Map 15:8 Reserved June 2009 – Revision 1.5 Pericom Semiconductor 5Port-8Lane PCI Express Switch TYPE DESCRIPTION RO Reset to 0000h. When set, it indicates that any entry of the Port Arbitration Table is written by software. This bit is cleared when hardware finishes loading values stored in RO the Port Arbitration Table after the bit of “ ...

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... Phase Phase [31] [30] June 2009 – Revision 1.5 Pericom Semiconductor TYPE DESCRIPTION When set, the programmed Port Arbitration Table is applied to the hardware. This bit always returns 0b when read. RW Reset to 0b. This field is used to configure the Port Arbitration by selecting one of the supported Port Arbitration schemes ...

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... CAPABILITY VERSION – OFFSET 20Ch BIT FUNCTION 19:16 Capability Version 7.2.101 NEXT ITEM POINTER REGISTER – OFFSET 20Ch BIT FUNCTION Next Capability 31:20 Offset June 2009 – Revision 1.5 Pericom Semiconductor Phase Phase Phase Phase [11:10] [9:8] [7:6] [5:4] Phase ...

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... BIT FUNCTION 0 System Allocated 31:1 Reserved June 2009 – Revision 1.5 Pericom Semiconductor 5Port-8Lane PCI Express Switch TYPE DESCRIPTION It indexes the power budgeting data reported through the data register. When 00h, it selects D0 Max power budget RW When 01h, it selects D0 Sustained power budget Other values would return zero power budgets, which means not supported Reset to 00h ...

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... ClkIn Duty cycle of input clock Rise/Fall time of input clock Differential input voltage swing SW a. RCUI (Reference Clock Unit Interval) refers to the reference clock period June 2009 – Revision 1.5 Pericom Semiconductor 5Port-8Lane PCI Express Switch Min Typical Max. - 100 (peak-to-peak) 800 ...

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... Hot Plug events that take place on the slots. Upon receiving of the interrupt events, the system software can use the Hot Plug Capability registers to respond to these events. June 2009 – Revision 1.5 Pericom Semiconductor 5Port-8Lane PCI Express Switch Page ...

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... Type 31-28 RO 27- June 2009 – Revision 1.5 Pericom Semiconductor 5Port-8Lane PCI Express Switch Register Selected Operation Boundary Scan Drives / receives off-chip test data Boundary Scan Samples inputs / pre-loads outputs Bypass Tri-states output and I/O pins except TDO pin Bypass ...

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... GPIO[ GPIO[ GPIO[ GPIO[ GPIO[ GPIO[ PWR_IND[1] June 2009 – Revision 1.5 Pericom Semiconductor 5Port-8Lane PCI Express Switch Ball Location Type H15 Input P11 Output2 P12 Input P13 Output2 N14 Input L14 Output2 K14 Input H14 Input G14 Bidir D16 ...

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... MRL_PDC[2] 48 MRL_PDC[3] 49 PWR_ENA[1] 50 PWR_ENA[2] 51 PWR_ENA[3] 52 PWR_FLT[1] 53 PWR_FLT[2] 54 PWR_FLT[3] 55 LANEACT[0] 56 LANEACT[1] 57 LANEACT[2] 58 LANEACT[3] 59 EECLK 60 EEPD 61 June 2009 – Revision 1.5 Pericom Semiconductor 5Port-8Lane PCI Express Switch Ball Location Type E1 Output2 F1 Output2 G3 Output2 G1 Output2 H1 Output2 F2 Input F3 Input G2 Input H3 Input J3 Input K3 Input L3 Output2 M3 Output2 ...

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... PI7C9X20508GP forwards power management messages to the upstream Switches or root complex. PI7C9X20508GP also supports ASPM (Active State Power Management) to facilitate the link power saving. PI7C9X20508GP supports beacon generation and WAKEUP_L signal. June 2009 – Revision 1.5 Pericom Semiconductor 5Port-8Lane PCI Express Switch Page PI7C9X20508GP TM ...

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... VTT: termination power supply for PCI Express Interface In order to support auxiliary power management fully recommended to have VDDC and VDDCAUX separated. The typical power consumption of PI7C9X20508GP is about 1.0 watt. June 2009 – Revision 1.5 Pericom Semiconductor 5Port-8Lane PCI Express Switch -65 -40 -0.3v to 3.0v -0 ...

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... Minimum swing assumes LoDrv = 1, HiDrv = 0 and Dtx =1100 c. Max swing assumes LoDrv = 0, HiDrv = 1, Dtx = 0010, VTT = 1. measured between 20% and 80% points. Will depend on package characteristics. e. Measured using PCI Express Compliance Pattern June 2009 – Revision 1.5 Pericom Semiconductor 5Port-8Lane PCI Express Switch Min Typical 400 ...

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... Over a frequency range of 50 MHz to 1.25 GHz. b. Over a frequency range of 50 MHz to 1.25 GHz. c. Assuming synchronized bit streams at the respective receiver inputs. d. This is a function of beacon frequency June 2009 – Revision 1.5 Pericom Semiconductor 5Port-8Lane PCI Express Switch Min Typical 170 ...

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... The package of PI7C9X20508GP is a 17mm x 17mm PBGA (256 Pin) package. The ball pitch is 1.0mm and the ball size is 0.5mm. The following are the package information and mechanical dimension: Figure 13-1 Bottom view drawing June 2009 – Revision 1.5 Pericom Semiconductor 5Port-8Lane PCI Express Switch Page PI7C9X20508GP ...

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... Figure 13-2 Package outline drawing June 2009 – Revision 1.5 Pericom Semiconductor 5Port-8Lane PCI Express Switch Page PI7C9X20508GP TM GreenPacket Family Datasheet ...

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... ORDERING INFORMATION Part Number □ PI7C9X20508GP NDE PI 7C 9X20508GP ND E June 2009 – Revision 1.5 Pericom Semiconductor Temperature Range Package 256-pin PBGA (Industrial Temperature) 17mm x 17mm Blank=Standard E=Pb-Free and Green Package Code Blank=Standard =Revision Device Type Device Number Family PI=Pericom ...