PSD303B-70M STMicroelectronics, PSD303B-70M Datasheet - Page 15

• Manufacturer Part Number: PSD303B-70M
• Description: MCU 8BIT PROGRM 70NS 44-PQFP
• Manufacturer: STMicroelectronics

Specifications of PSD303B-70M

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 44-MQFP, 44-PQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.0
Operating
Modes (MCU
Configurations)
(cont.)
12
PSD3XX Family
9.0
Programmable
Address
Decoder (PAD)
Table 3. Bus and Port Configuration Options
The PSD3XX contains two programmable arrays, referred to as PAD A and PAD B
(Figure 4). PAD A is used to generate chip select signals derived from the input address to
the internal EPROM blocks, SRAM, I/O ports, and Track Mode signals.
PAD B outputs to Ports B and C for off-chip usage. PAD B can also be used to extend the
decoding to select external devices or as a random logic replacement.
PAD A and PAD B receive the same inputs. The PAD logic is configured by PSDsoft
based on the designer’s input. The PAD’s non-volatile configuration is stored in a
re-programmable CMOS EPROM. Windowed packages are available for erasure by the
user. See Table 4 for a list of PAD A and PAD B functions.
8-bit Data Bus
Port A
Port B
AD0/A0–AD7/A7
AD8/A8–AD15/A15
16-bit Data Bus
Port A
Port B
AD0/A0–AD7/A7
AD8/A8–AD15/A15
Multiplexed Address/Data
I/O or low-order address
lines or Low-order multiplexed
address/data byte
I/O and/or CS0–CS7
Low-order multiplexed
address/data byte
High-order address
bus byte
I/O or low-order address
lines or low-order multiplexed
address/data byte
I/O and/or CS0–CS7
Low-order multiplexed
address/data byte
High-order multiplexed
address/data byte
Non-Multiplexed Address/Data
D0–D7 data bus byte
I/O and/or CS0–CS7
Low-order address bus byte
High-order address bus byte
Low-order data bus byte
High-order data bus byte
Low-order address bus byte
High-order address bus byte