HCTL-2032-SC Avago Technologies US Inc., HCTL-2032-SC Datasheet - Page 6

• Manufacturer Part Number: HCTL-2032-SC
• Description: IC DECODER/COUNTER 32BIT 32-SOIC
• Manufacturer: Avago Technologies US Inc.
• Type: Quadrature Decoder/Counter Interface ICr

Specifications of HCTL-2032-SC

• Package / Case: 32-SOIC (7.5mm Width)
• Applications: Encoder to Microprocessor
• Interface: 8-Bit Tristate
• Voltage - Supply: 4.5 V ~ 5.5 V
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 516-1885-5; HCTL-2032-SC

Functional Pin Description
Table 4. Functional Pin Descriptions

Symbol
V
V
CLK
CHA
CHA
CHB
CHB
CHI
CHI
RSTN
RSTN
OEN
SEL
SEL
EN
EN
X/Y
CNTDEC
CNTDEC
U/Dx
U/Dy
DD
SS
1
2
Y
1
2
X
Y
X
Y
X
X
Y
X
Y
HCTL
2032/
2032-SC
1
18
5
15
16
14
13
17
19
12
11
7
6
26
2
3
32
27
28
8
9
Pin
HCTL
2022
1
12
3
10
NC
9
NC
11
NC
8
NC
5
4
17
NC
NC
NC
NC
NC
6
NC
Description
Power Supply
Ground
CLK is a Schmitt-trigger input for the external clock signal.
CHA
from a quadrature-encoded source, such as incremental optical shaft encoder. Two
channels, A and B, nominally 90 degrees out of phase, are required. CHA
are the 1st axis and CHA
CHI
from an incremental optical shaft encoder.
This active low Schmitt-trigger input clears the internal position counter and the
position latch. It also resets the inhibit logic. RST
respect to any other input signals. RST
to reset the 2nd axis counter.
This CMOS active low input enables the tri-state output buffers. The OE/, SEL1, and
SEL2 inputs are sampled by the internal inhibit logic on the falling edge of the clock
to control the loading of the internal position data latch.
These CMOS inputs directly controls which data byte from the position latch is en-
abled into the 8-bit tri-state output buffer. As in OE/ above, SEL
trol the internal inhibit logic.
These CMOS control pins are set to high or low to activate the selected count mode
before the decoding begins.
Select the 1
high bit enables the 2
A pulse is presented on this LSTTL-compatible output when the quadrature decod-
er (4x/2x/1x) has detected a state transition. CNTDECX is for 1
is for 2
This LSTTL-compatible output allows the user to determine whether the IC is count-
ing up or down and is intended to be used with the CNTDEC and CNTCAS outputs.
The proper signal U (high level) or D/ (low level) will be present before the rising
edge of the CNTDEC and CNTCAS outputs.
SEL1
X
X
EN1
and CHI
, CHA
0
1
0
1
0
1
0
1
nd
axis.
Y
, CHB
st
Y
or 2
SEL2
are Schmitt-trigger inputs that accept the outputs of Index channel
EN2
1
1
0
0
X
0
0
1
1
nd
, and CHB
axis data to be read. Low bit enables the 1
nd
Y
axis data.
and CHB
MSB
D4
Y
On
4x
are Schmitt-trigger inputs that accept the outputs
Y
Count Modes
Illegal Mode
are the 2nd axis.
BYTE SELECTED
X
2ND
/ is to reset the 1st axis counter and RST
D3
On
2x
X
/ and RST
3RD
D2
On
1x
Y
/ are asynchronous with
LSB
st
D1
1
axis and CNTDECY
and SEL
st
axis data, while
X
2
and CHB
also con-
Y
/ is
X