HCTL-2032-SC Avago Technologies US Inc., HCTL-2032-SC Datasheet - Page 17

• Manufacturer Part Number: HCTL-2032-SC
• Description: IC DECODER/COUNTER 32BIT 32-SOIC
• Manufacturer: Avago Technologies US Inc.
• Type: Quadrature Decoder/Counter Interface ICr

Specifications of HCTL-2032-SC

• Package / Case: 32-SOIC (7.5mm Width)
• Applications: Encoder to Microprocessor
• Interface: 8-Bit Tristate
• Voltage - Supply: 4.5 V ~ 5.5 V
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 516-1885-5; HCTL-2032-SC

Figure 16. Decode and Casade Output Diagram (4x)

Cascade Considerations
The HCTL-2032 / 2032-SC ‘s cascading system allows for
position reads of more than four bytes. These reads can
be accomplished by latching all the bytes and then read-
ing the bytes sequentially over the 8-bit bus. It is assumed
here that, externally, a counter followed by a latch is used
to count any count that exceeds 32 bits. This configura-
tion is compatible with the HCTL-2032 / 2032-SC internal
counter/latch combination.
Consider the sequence of events for a read cycle that
starts as the HCTL-2032 / 2032-SC ‘s internal counter rolls
over. On the rising clock edge, count data is updated in
the internal counter, rolling it over. A count-cascade pulse
(CNT
ing clock edge (t
tion delays through the external counters and registers.
Meanwhile, with SEL and OE low to start the read, the in-
ternal latches are inhibited at the falling edge and do not
update again till the inhibit is reset.
CNT DCDR
COUNT
CHA FLT
CHB FLT
U/Dbar
CLK
CNT cas
CAS
) will be generated with some delay after the ris-
CHD
). There will be additional propaga-
FFFFFFFDh
(HCTL-2032 / 2032-SC only)
FFFFFFFEh
FFFFFFFh
If the CNT
and this count gets latched a major count error will oc-
cur. The count error is because the external latches get
updated when the internal latch is inhibited.
Valid data can be ensured by latching the external coun-
ter data when the high byte read is started (SEL and OE
low). This latched external byte corresponds to the count
in the inhibited internal latch. The cascade pulse that oc-
curs during the clock cycle when the read begins gets
counted by the external counter and is not lost.
For example, suppose the HCTL-2032 / 2032-SC count is
at FFFFFFFFh and an external counter is at F0h, with the
count going up. A count occurring in the HCTL-2032 /
2032-SC will cause the counter to roll over and a cascade
pulse will be generated. A read starting on this clock cy-
cle will show FFFFFFFFh from the HCTL-2032 / 2032-SC.
The external latch should read F0h, but if the host latches
the count after the cascade signal propagates through,
the external latch will read F1h.
00000000h
CAS
pulse now toggles the external counter
FFFFFFFEh
FFFFFFFh