HCTL-2022 Avago Technologies US Inc., HCTL-2022 Datasheet - Page 8

• Manufacturer Part Number: HCTL-2022
• Description: QUADRATURE DECODER/COUNTER INTER
• Manufacturer: Avago Technologies US Inc.
• Type: Quadrature Decoder/ Counter Interface ICr

Specifications of HCTL-2022

• Package / Case: 20-DIP (0.300", 7.62mm)
• Mounting Type: Through Hole
• Voltage - Supply: 4.5 V ~ 5.5 V
• Applications: Encoder to Microprocessor
• Interface: 8-Bit Tristate
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: Q2414340A

Switching Characteristics
Table 5. Switching Characteristics
Max/Min specifications at V
Notes
1. tclk - max delay (item 20/21) + min delay (item 22/23)
2. tclk - max delay (item 22/23) + min delay (item 20/21)

Symbol


3
4




9
0


3
4




9
0


3
4




9
30
3
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CLK
CHH
CD
ODE
ODZ
SDV
XNYDV
CLH
SS
OS
XNYS
SH
OH
XNYH
RST
DCD
DSD
DOD
DXNYD
UDDX
UDDY
CHXD
CHYD
CLXD
CLYD
UDXH
UDYH
UDCXS
UDCYS
UDCXH
UDCYH
Description
Clock Period
Pulse width, clock high
Delay time, rising edge of clock to valid, updated count information on D0-
Delay time, OEN fall to valid data
Delay time, OEN rise to Hi-Z state on D0-
Delay time, SEL0~SEL valid to stable, selected data byte
(delay to High Byte = delay to Low Byte)
Delay time, XNY valid to stable, selected data byte.
Pulse width, clock low
Setup time, SEL~SEL before clock fall
Setup time, OEN before clock fall
Setup time, XNY before clock fall
Hold time, SEL~SEL after clock fall
Hold time, OEN after clock fall
Hold time, XNY after clock fall
Pulse width, RSTNX~RSTNY low
Hold time, last position count stable on D0- after clock rise
Hold time, last data byte stable after next SEL state change
Hold time, data byte stable after OEN rise
Hold time, data byte stable after XNY change
Delay time, U/DNX valid after clock rise
Delay time, U/DNY valid after clock rise
Delay time, CNTDECX or CNTCASX high after clock rise
Delay time, CNTDECY or CNTCASY high after clock rise
Delay time, CNTDECX or CNTCASX low after clock fall
Delay time, CNTDECY or CNTCASY low after clock fall
Hold time, U/DNX stable after clock rise
Hold time, U/DNY stable after clock rise
Setup time, U/DNX valid before CNTDECX or CNTCASX rise
Setup time, U/DNY valid before CNTDECY or CNTCASY rise
Hold time, U/DNX stable after CNTDECX or CNTCASX rise
Hold time, U/DNY stable after CNTDECY or CNTCASY: rise
DD
= 5V ± 5%; T
A
= -40 to 100°C, C
L
= 40 pf
Min.
/f




0
0
0
0




4
4
4
4
4
4


Note 
Note 
Note 
Note 
Max.
33
3
9
9
9
9
9
9
3
3
3
3
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns