PX1011BI-EL1/G,551 NXP Semiconductors, PX1011BI-EL1/G,551 Datasheet - Page 18

• Manufacturer Part Number: PX1011BI-EL1/G,551
• Description: IC PCI-EXPRESS X1 PHY 81-LFBGA
• Manufacturer: NXP Semiconductors

Specifications of PX1011BI-EL1/G,551

• Package / Case: 81-LFBGA
• Applications: PCI Express MAX to PCI Express PHY
• Interface: JTAG
• Voltage - Supply: 1.2 V
• Mounting Type: Surface Mount
• Input Voltage Range (max): 0.31 V
• Maximum Operating Temperature: + 85 C
• Maximum Power Dissipation: 300 mW
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 1.2 V
• Supply Current (max): 28 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935282114551; PX1011BI-EL1/G-S; PX1011BI-EL1/G-S

NXP Semiconductors
PX1011B_4
Product data sheet
8.12 Setting negative disparity
8.13 JTAG boundary scan interface
To set the running disparity to negative, the MAC asserts TXCOMP for one clock cycle
that matches with the data that is to be transmitted with negative disparity.
Joint Test Action Group (JTAG) or IEEE 1149.1 is a standard, specifying how to control
and monitor the pins of compliant devices on a printed-circuit board. This standard is
commonly known as ‘JTAG Boundary Scan’.
This standard defines a 5-pin serial protocol for accessing and controlling the signal levels
on the pins of a digital circuit, and has some extensions for testing the internal circuitry on
the chip itself, which is beyond the scope of this data sheet.
Access to the JTAG interface is provided to the customer for the sole purpose of using
boundary scan for interconnect test verification between other compliant devices that may
reside on the board. Using JTAG for purposes other than boundary scan may produce
undesired effects.
The JTAG interface is a 3.3 V CMOS signaling. JTAG TRST_N must be asserted LOW for
normal device operation. If JTAG is not planned to be used, it is recommended to
pull down TRST_N to V
Fig 16. Setting negative disparity
TXDATA[7:0]
TX_P, TX_N
TXCOMP
TXCLK
data
valid data
Rev. 04 — 4 September 2009
SS
.
K28.5
K28.5
PCI Express stand-alone X1 PHY
K28.5
K28.5
byte transmitted
with negative disparity
K28.5
K28.5
PX1011B
© NXP B.V. 2009. All rights reserved.
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