LTC4306IUFD#TRPBF Linear Technology, LTC4306IUFD#TRPBF Datasheet - Page 8
![no-image](/images/manufacturer_photos/0/3/388/linear_technology_sml.jpg)
LTC4306IUFD#TRPBF
Manufacturer Part Number
LTC4306IUFD#TRPBF
Description
IC MUX 4CH 2-WIRE BUS 24-QFN
Manufacturer
Linear Technology
Datasheet
1.LTC4306CUFDPBF.pdf
(20 pages)
Specifications of LTC4306IUFD#TRPBF
Applications
Multiplexer with Amplifier
Interface
SMBus (2-Wire/I²C)
Voltage - Supply
2.2 V ~ 5.5 V
Package / Case
24-QFN
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
OPERATIO
LTC4306
Register 0 (00h)
Note: Masters write to Register 0 to reset the fault circuitry after a fault
has occurred and been resolved. Because Register 0 is Read-Only, no
other functionality is affected.
* For Type, “R/W” = Read Write, “R” = Read Only
8
Control Register Bit Definitions
BIT NAME
d7 Downstream
d6 ALERT1 Logic State
d5 ALERT2 Logic State
d4 ALERT3 Logic State
d3 ALERT4 Logic State
d2 Failed Connection
d1 Latched Timeout
d0 Timeout Real Time
Connected
Attempt
U
TYPE* DESCRIPTION
R
R
R
R
R
R
R
R
Indicates if upstream bus is connected
to any downstream buses
0 = upstream bus disconnected from
all downstream buses
1 = upstream bus connected to one or
more downstream buses
Logic state of ALERT1 pin, noninverting
Logic state of ALERT2 pin, noninverting
Logic state of ALERT3 pin, noninverting
Logic state of ALERT4 pin, noninverting
Indicates if an attempt to connect to a
downstream bus failed because the
“Connection Requirement” bit in
Register 2 was low and the
downstream bus was low
0 = Failed connection attempt occurred
1 = No failed attempts at connection
occurred
Latched bit indicating if a timeout has
occurred and has not yet been cleared.
0 = no latched timeout
1 = latched timeout
Indicates real-time status of Stuck Low
Timeout Circuitry
0 = no timeout is occurring
1 = timeout is occurring
Register 1 (01h)
* For Type, “R/W” = Read Write, “R” = Read Only
d3-d2 Reserved
BIT
d7
d6
d5
d4
d1
d0
NAME
Upstream
Accelerators
Enable
Downstream
Accelerators
Enable
GPIO1 Output
Driver State
GPIO2 Output
Driver State
GPIO1 Logic
State
GPIO2 Logic
State
TYPE* DESCRIPTION
R/W
R/W
R/W
R/W
R
R
R
Activates upstream rise time
accelerator currents
0 = upstream rise time accelerator
currents inactive (default)
1 = upstream rise time accelerator
currents active
Activates downstream rise time
accelerator currents
0 = downstream rise time accelerator
currents inactive (default)
1 = downstream rise time accelerator
currents active
GPIO1 output driver state,
noninverting, default = 1
GPIO2 output driver state,
noninverting, default = 1
Not Used
Logic state of GPIO1 pin,
noninverting
Logic state of GPIO2 pin,
noninverting
4306f