LTC4306 Linear Technology, LTC4306 Datasheet
LTC4306
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LTC4306 Summary of contents
Page 1
... Driving the ENABLE pin low restores all features to their default states. Three address pins provide 27 distinct addresses. The LTC4306 is available in 24-lead QFN (4mm × 5mm) and SSOP packages. All other trademarks are the property of their respective owners. Patent pending. ...
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... A CC CONDITIONS Downstream Connected, SCL Bus Low, SDA Bus High 0V, V ENABLE CC LTC4306C ............................................... 0°C to 70°C LTC4306I ............................................. –40°C to 85°C SSOP ................................................. –65°C to 150°C QFN ................................................... –65°C to 125°C SSOP ................................................................ 300°C TOP VIEW 1 24 ALERT2 SCL3 2 SCL2 ...
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... I = 5mA 2.7V GPIO –200µA, V GPIO 0V, 5.5V, V GPIO 2.7V, 5.5V CC TIMSET1 TIMSET1 TIMSET1 3mA 2.7V ALERT 0V, 5.5V ALERT V = 0V, 5.5V ALERT1-4 LTC4306 MIN TYP ● 100 175 ● 0.8 1 ● ● = 2.7V 0.18 ● ● ● ● 70 110 ● ...
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... BUS 50 150 = where positive offset voltage. LOW2 LOW the offset voltage when the LTC4306 is driving the upstream is the offset voltage when the OS,DOWN-BUF and V OS,UP-BUF OS,DOWN-BUF and bus pull-up current. CC and still convert the address correctly. ADR(FLOAT) MAX UNITS 1 ...
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... V = 3.3V CC 150 100 BUS PULL-UP CURRENT (mA) 4306 G05 I vs Temperature BOOST 3. 100 125 –50 – TEMPERATURE (°C) 4306 G07 LTC4306 100 125 4306 G03 4306f 5 ...
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... Fault Alert Inputs, Channels 1-4. Devices on each of the four output channels can pull their respective pin low to indicate that a fault has occurred. The LTC4306 then pulls the ALERT low to pass the fault indication on to the host. See Operation section below for the details of how ALERT is set and cleared ...
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... BLOCK DIAGRA www.DataSheet4U.com W LTC4306 4306f 7 ...
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... LTC4306 U OPERATIO Control Register Bit Definitions Register 0 (00h) BIT NAME TYPE* DESCRIPTION d7 Downstream R Connected www.DataSheet4U.com d6 ALERT1 Logic State R d5 ALERT2 Logic State R d4 ALERT3 Logic State R d3 ALERT4 Logic State R d2 Failed Connection R Attempt d1 Latched Timeout R d0 Timeout Real Time R Note: Masters write to Register 0 to reset the fault circuitry after a fault has occurred and been resolved ...
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... These bits give the logic state of disconnected downstream buses to the master, so that the master can choose not to connect to a low downstream bus. A given bit is a “don’t care” if its associated downstream bus is already connected to the upstream bus. LTC4306 TYPE* DESCRIPTION R/W Sets and indicates state of FET switches connected to downstream ...
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... Block Diagram will only connect to downstream channels whose corresponding Bus Logic State bits in register 3 are high at the moment that it receives the connection com- mand. If the LTC4306 is commanded to connect to mul- tiple channels at once, it will only connect to the channels that are high. Masters can override this feature by setting the Connection Requirement bit of register 2 high ...
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... ALERT Functionality and Fault Resolution is less than V . Doing so CC When a fault occurs, the LTC4306 pulls the ALERT pin low, as described previously. The procedure for resolving faults depends on the type of fault master on the upstream bus is communicating with devices on a down- stream bus via the Upstream-Downstream Buffer cir- cuitry— ...
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... After the master broadcasts the Alert Response Address (ARA), the LTC4306 will respond with its address on the SDAIN line and release the ALERT pin. The ALERT line will also be released if the LTC4306 is addressed by the master. The ALERT signal will not be pulled low again until a different type of fault has occurred or the original fault is www ...
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... Data Byte is written into the register selected by bits r1 and r0 on the Stop Bit. General Purpose Input/Outputs (GPIOs) The LTC4306 provides two general purpose input/output pins (GPIOs) that can be configured as logic inputs, open- drain outputs or push-pull outputs. The GPIO1 and GPIO2 ...
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... GPIOs. If the LTC4306 is trying to write a high to a GPIO pin, but the pin’s actual logic state is low, then the LTC4306 knows that the low is being forced by an external device. Glitch Filters voltage ...
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... U U APPLICATIO S I FOR ATIO Design Example A typical LTC4306 application circuit is shown in Figure 5. The circuit illustrates the level-shifting, multiplexer/switch and capacitance buffering features of the LTC4306. In this application, the LTC4306 V bus 1 are powered from a 3.3V supply voltage; down- stream bus 4 is powered from 5V, and the upstream bus is powered from 2 ...
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... CC at the moment of connection/disconnection. Note that pull-up resistor, R17, on ALERT4 should be located on the backplane and not the I/O card to ensure proper operation of the LTC4306 when the I/O card is not present. The pull- up resistors on SCL4 and SDA4, R15 and R16 respec during tively, may be located on the I/O card, provided that ...
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... GPI01 9 GPI02 SCL3 SDA3 ALERT3 12 ADR2 OPEN ADR1 10 ADR0 SCL4 SDA4 3 GND ALERT4 ADDRESS = 1010 000 Figure 6. Nested Addressing Application LTC4306 0.01µF 10k 10k 10k 16 17 TEMPERATURE SENSOR 18 ADDRESS = 1001 000 R9 R10 R11 10k 10k 10k 21 20 TEMPERATURE ...
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... R4 R5 10k 10k µ www.DataSheet4U.com 10k V CC OPEN SCLIN 2 SDAIN 5 ENABLE R18 200k 1 ALERT LTC4306UFD 12 ADR2 11 ADR1 10 ADR0 3 GND BACKPLANE CARD ADDRESS = 1010 000 CONNECTOR CONNECTOR Figure 7. Hot-Swapping Application C1 0.01µ 10k 10k 10k SCL1 ...
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... FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. LTC4306 2.65 ± 0.10 (2 SIDES 0.115 0.75 ± ...
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... R4 R5 10k 10k 10k 10k V CC SCLIN SDA1 ALERT1 SDAIN ENABLE ALERT SCL2 SDA2 READY ALERT2 V CC LTC4306UFD GPI01 R1 LED 1k GPI02 SCL3 SDA3 ALERT3 ADR2 OPEN ADR1 ADR0 SCL4 SDA4 GND ALERT4 ADDRESS = 1010 000 Figure 8. Downstream Side Hot-Swapping Application 2 TM ...