LTC4305IGN Linear Technology, LTC4305IGN Datasheet - Page 13

• Manufacturer Part Number: LTC4305IGN
• Description: IC BUFFER BUS 2WR ADDRESS 16SSOP
• Manufacturer: Linear Technology

Specifications of LTC4305IGN

• Applications: Multiplexer with Amplifier
• Interface: SMBus (2-Wire/I²C)
• Voltage - Supply: 2.2 V ~ 5.5 V
• Package / Case: 16-SSOP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

OPERATIO
regardless of their individual address settings. The mass
write can be masked by setting the mass write enable bit
of register 2 to zero. Address (0001 100) is the SMBus
Alert Response Address. Figure 3 shows data transfer
over a 2-wire bus.
Supported Commands
Users must write to the LTC4305 using the SMBus Write
Byte protocol and read from it using the Read Byte
protocol. During fault resolution, the LTC4305 also
supports the Alert Response Address protocol. The
formats for these protocols are shown in Figure 4. Users
must follow the Write Byte protocol exactly to write to the
LTC4305; if a Repeated Start Bit is issued before a Stop
Bit, the LTC4305 ignores the attempted write, and its
control bits remain in their preexisting state. When users
follow the WriteByte protocol exactly, the new data con-
tained in the Data Byte is written into the register selected
by r1 and r0 on the Stop Bit.
SDA
SCL
U
START
1
CONDITION
START
10 a4 - a0
ADDRESS
S
SLAVE
7
START
ADDRESS
1
a6 - a0
WR
1 - 7
1
0
10 a4 - a0
ADDRESS
SLAVE
ACK
7
1
S
0
S
1
R/W
8
Figure 4. Protocols Accepted by LTC4305
Figure 3. Data Transfer Over I
XXXXXX r1 r0
REGISTER
0001 100
WR
1
0
8
7
ACK
9
ALERT RESPONSE ADDRESS PROTOCOL
ACK
1
S
0
Rd
1
1
WRITE BYTE PROTOCOL
ACK
READ BYTE PROTOCOL
1
S
0
1 - 7
XXXXXX r1 r0
REGISTER
d7 - d0
ACK
DATA
START
8
1
S
0
1
DEVICE ADDRESS
Glitch Filters
The LTC4305 provides glitch filters on the SDAIN and
SCLIN pins as required by the I
Specification. The filters prevent signals of up to 50ns
(minimum) time duration and rail-to-rail voltage magni-
tude from passing into the two-wire bus digital interface
circuitry.
Fall Time Control
Per the I
two-wire bus digital interface circuitry provides fall time
control when forcing logic lows onto the SDAIN bus. The
fall time always meets the limits:
where t
capacitance in pF. Whenever the upstream-downstream
buffer circuitry is active, its output signal will meet the fall
time requirements, provided that its input signal meets the
fall time requirements.
8
10 a4 - a0
ADDRESS
(20 + 0.1 • C
SLAVE
ACK
1
S
0
7
8
ACK
2
9
f
C/SMBus
is the fall time in ns and C
2
RD
d7 - d0
1
1
DATA
BYTE
ACK
C Fast Mode (400kHz) Specification, the
M
8
1
1
1 - 7
ACK
B
1
S
0
) < t
d7 - d0
1
P
DATA
ACK
1
S
0
f
d7 - d0
< 300ns
DATA
BYTE
8
8
STOP
1
ACK
9
ACK
M
1
1
2
C Fast Mode (400kHz)
CONDITION
B
STOP
STOP
4305 F04
is the equivalent bus
1
P
4305 F03
LTC4305
13
4305f