LTC4305IGN Linear Technology, LTC4305IGN Datasheet
LTC4305IGN
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LTC4305IGN Summary of contents
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... Three address pins provide 27 distinct addresses. The LTC4305 is available in 16-lead (4mm × 5mm) DFN and SSOP packages. , LTC and LT are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Patent Pending ...
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... SCL1 11 READY 10 ADR2 9 ADR1 = 125°C JMAX ORDER PART NUMBER 4305 LTC4305CGN 4305 LTC4305IGN ● The denotes specifications which apply over the full specified temperature = 25° 3.3V unless otherwise noted CONDITIONS Downstream Connected, V SCL Bus Low, SDA Bus High 5.5V ...
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ELECTRICAL CHARACTERISTICS range, otherwise specifications are SYMBOL PARAMETER Power Supply/Start-Up V ENABLE Falling Threshold Voltage ENABLE Threshold Hysteresis Voltage EN HYST t ENABLE Delay, On-Off PHL EN t ENABLE Delay, Off-On PLH EN I ...
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LTC4305 ELECTRICAL CHARACTERISTICS range, otherwise specifications are at T SYMBOL PARAMETER Interface V ADR0–2 Input High Voltage ADR(H) V ADR0–2 Input Low Voltage ADR(L) I ADR0–2 Logic Low Input Current ADR(IN ADR0–2 Logic High Input ...
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W U TYPICAL PERFOR A CE CHARACTERISTICS Buffer Circuitry t PHL vs Temperature 120 100 100 125 –50 – TEMPERATURE (°C) 4305 G01 ...
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LTC4305 CTIO S ALERT1–ALERT2 (Pins 14, 1): Fault Alert Inputs, Channels 1–2. Devices on each of the two output channels can pull their respective pin low to indicate that a fault has occurred. The LTC4305 ...
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W BLOCK DIAGRA INACC UPSTREAM DOWNSTREAM SLEW RATE BUFFERS DETECTOR SDAIN 3 INACC UPSTREAM DOWNSTREAM SLEW RATE BUFFERS DETECTOR SCLIN 5 READY 11 + SCLIN 100ns GLITCH FILTER – 1.6V/1.52V + SDAIN 100ns GLITCH FILTER – LIM ...
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LTC4305 U OPERATIO Control Register Bit Definitions Register 0 (00h) BIT NAME TYPE* DESCRIPTION d7 Downstream R Indicates if upstream bus is connected Connected to any downstream buses 0 = upstream bus disconnected from all downstream buses 1 = upstream ...
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U OPERATIO Register 2 (02h) BIT NAME TYPE* DESCRIPTION d7 Reserved R Not Used d6 Reserved R Not Used d5 Connection R/W Sets logic requirements for Requirement downstream buses to be connected to upstream bus 0 = Bus Logic State ...
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LTC4305 U OPERATIO The LTC4305 is a 2-channel 2-wire bus multiplexer/ switch with bus buffers to provide capacitive isolation between the upstream bus and downstream buses. Mas- ters on the upstream 2-wire bus (SDAIN and SCLIN) can command the LTC4305 ...
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U OPERATIO separated by the series combination of their switches’ on resistances. While neither, either or both downstream buses may be connected at the same time, logic high levels are corrupted if both downstream buses are active and both the ...
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LTC4305 U OPERATIO disconnects the downstream buses from the upstream bus by de-biasing the Upstream-Downstream Buffers. Note that the downstream switches remain in their exist- ing state. The Timeout Real Time bit of register 0 indicates the real-time status of ...
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U OPERATIO regardless of their individual address settings. The mass write can be masked by setting the mass write enable bit of register 2 to zero. Address (0001 100) is the SMBus Alert Response Address. Figure 3 shows data transfer ...
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LTC4305 U OPERATIO 2 Table 1. LTC4305 I C Device Addressing HEX DEVICE DESCRIPTION ADDRESS h a6 Mass Write BC 1 Alert Response ...
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U U APPLICATIO S I FOR ATIO Design Example A typical LTC4305 application circuit is shown in Figure 5. The circuit illustrates the level-shifting, multiplexer/switch and capacitance buffering features of the LTC4305. In this application, the LTC4305 V voltage and ...
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LTC4305 U U APPLICATIO S I FOR ATIO Level Shifting Considerations In Figure 5, the LTC4305 V voltage is less than or equal CC to both of the downstream bus pull-up voltages, so both downstream buses can be active at ...
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U U APPLICATIO S I FOR ATIO 10k 10k MICRO- CONTROLLER 10k V CC OPEN BACKPLANE BACKPLANE CONNECTOR SCLIN 3 SDAIN 6 ENABLE R4 200k ...
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LTC4305 PACKAGE DESCRIPTIO 4.50 ±0.05 3.10 ±0.05 2.44 ±0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS PIN 1 TOP MARK (SEE NOTE 6) 0.200 REF NOTE: 1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WJGD-2) IN JEDEC PACKAGE ...
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... FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. ...
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... Addressable 2-Wire Bus Buffer LTC4303/LTC4304 Hot Swappable 2-Wire Bus Buffer with Stuck Bus Recovery LTC4306 4-Channel 2-Wire Multiplexer with Capacitance Buffering ThinSOT is a trademark of Linear Technology Corporation. Linear Technology Corporation 20 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 FAX: (408) 434-0507 ● ...