PI7C9X20505GPBNDE Pericom Semiconductor, PI7C9X20505GPBNDE Datasheet - Page 28

• Manufacturer Part Number: PI7C9X20505GPBNDE
• Description: IC PCIE PACKET SWITCH 256BGA
• Manufacturer: Pericom Semiconductor
• Series: GreenPacket™r

Specifications of PI7C9X20505GPBNDE

• Applications: Data Transport
• Interface: Advanced Configuration Power Interface (ACPI)
• Package / Case: 256-PBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply: -

June 2009 – Revision 1.5
Pericom Semiconductor
ADDRESS
19h
20h
22h
24h
80h: Bit [29:28]
84h (Port 4)
84h: Bit [31:24]
F0h (Port 0)
F0h: Bit [28]
80h (Port 0)
80h: Bit[21]
144h (Port 0)
144h: Bit [4]
ECh (Port 0)
ECh: Bit [26:24]
154h (Port 0)
154h: Bit [7:1]
E0h (Port1)
E0h: Bit [24]
F0h (Port 1)
F0h: Bit [28]
80h (Port 1)
80h: Bit[21]
144h (Port 1)
144h: Bit [4]
ECh (Port 1)
ECh: Bit [26:24]
154h (Port 1)
154h: Bit [7:1]
E0h (Port 2)
E0h: Bit [24]
F0h (Port 2)
F0h: Bit [28]
80h (Port 2)
80h: Bit[21]
144h (Port 2)
144h: Bit [4]
ECh (Port 2)
ECh: Bit [26:24]
154h (Port 2)
154h: Bit [7:1]
PCI CFG
OFFSET
DESCRIPTION
Power Management Data for Port 4
Slot Clock Configuration for Port 0
Device specific Initialization for Port 0
LPVC Count for Port 0
Port Number for Port 0
VC0 TC/VC Map for Port 0
PCIe Capability Slot Implemented for Port 1
Slot Clock Configuration for Port 1
Device specific Initialization for Port 1
LPVC Count for Port 1
Port Number for Port 1
VC0 TC/VC Map for Port 1
PCIe Capability Slot Implemented for Port 2
Slot Clock Configuration for Port 2
Device specific Initialization for Port 2
LPVC Count for Port 2
Port Number for Port 2
VC0 TC/VC Map for Port 2
Page 28 of 81



















Bit [7:6]: PME Support for D2 and D1 states
Bit [15:8] – read only as Data register
Bit [1]: When set, the component uses the clock provided on the
connector
Bit [2]: When set, the DSI is required
Bit [3]: When set, the VC1 is allocated to LPVC of Egress Port 0
Bit [6:4]: It represents the logic port numbering for physical port
0
Bit [15:9]: When set, it indicates the corresponding TC is
mapped into VC0
Bit [0]: When set, the slot is implemented for Port 1
Bit [1]: When set, the component uses the clock provided on the
Bit [2]: When set, the DSI is required
Bit [3]: When set, the VC1 is allocated to LPVC of Egress Port 1
Bit [6:4]: It represents the logic port numbering for physical port
1
Bit [15:9]: When set, it indicates the corresponding TC is
mapped into VC0
Bit [0]: When set, the slot is implemented for Port 2
Bit [1]: When set, the component uses the clock provided on the
Connector
Bit [2]: When set, the DSI is required
Bit [3]: When set, the VC1 is allocated to LPVC of Egress Port 2
Bit [6:4]: It represents the logic port numbering for physical port
2
Bit [15:9]: When set, it indicates the corresponding TC is
mapped into VC0
Connector
5Port-5Lane PCI Express Switch
GreenPacket
PI7C9X20505GP
Datasheet
TM
Family