ADM1024ARUZ ON Semiconductor, ADM1024ARUZ Datasheet - Page 18

• Manufacturer Part Number: ADM1024ARUZ
• Description: IC MONITOR SYS TEMP/VOLT 24TSSOP
• Manufacturer: ON Semiconductor

Specifications of ADM1024ARUZ

• Applications: PC's, PDA's
• Interface: Serial
• Voltage - Supply: 2.8 V ~ 5.5 V
• Package / Case: 24-TSSOP
• Mounting Type: Surface Mount
• Temperature Sensor Function: Temp Sensor
• Output Type: Digital
• Package Type: TSSOP
• Operating Temperature (min): 0C
• Operating Temperature (max): 100C
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 5.5V
• Full Temp Accuracy: +/- 2 C , +/- 3 C
• Digital Output - Bus Interface: SMBus
• Digital Output - Number Of Bits: 10 bit
• Supply Voltage (max): 12 V
• Supply Voltage (min): 2.5 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: 0 C
• Supply Current: 1.4 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Limit Values
voltage, so the failure condition of interest is under−speed
due to electrical or mechanical failure. For this reason only,
low speed limits are programmed into the limit registers for
the fans. It should be noted that, since fan period rather than
speed is being measured, a fan failure interrupt will occur
when the measurement exceeds the limit value.
Monitoring Cycle Time
number of tachometer output pulses per revolution. Two
complete periods of the fan tachometer output (three rising
edges) are required for each fan measurement. Therefore, if
the start of a fan measurement just misses a rising edge, the
measurement can take almost three tachometer periods. In
order to read a valid result from the fan value registers, the
total monitoring time allowed after starting the monitoring
cycle should, therefore, be three tachometer periods of
FAN1 plus three tachometer periods of FAN2 at the lowest
normal fan speed.
monitoring cycle are started together, they are not
synchronized in any other way.
Fan Manufacturers
are listed below:
NMB Tech
9730 Independence Ave.
Chatsworth, California 91311
Phone: 818−341−3355; Fax: 818−341−8207
Mechatronics Inc.
P.O. Box 613
Preston, WA 98050
800−453−4569
Sanyo Denki, America, Inc.
468 Amapola Avenue
Torrance, CA 90501
310−783−5400
Table 5. Fan Speeds and Divisors
2410ML
2408NL
3108NL
3110KL
Fans in general will not over−speed if run from the correct
The monitoring cycle time depends on the fan speed and
Although the fan monitoring cycle and the analog input
Manufacturers of cooling fans with tachometer outputs
Models—Various sizes available with tachometer output option.
Models—109P Series
Model
Divisor RPM
÷ 1
÷ 2
÷ 4
÷ 8
2.36 in sq × 0.79 in; (60 mm sq × 20 mm)
2.36 in sq × 0.98 in; (60 mm sq × 25 mm)
3.15 in sq × 0.79 in; (80 mm sq × 20 mm)
3.15 in sq × 0.98 in; (80 mm sq × 25 mm)
Nominal RPM
Frame Size
8800
4400
2200
1100
Rev (ms)
13.64
27.27
54.54
6.82
Airflow
14–25
25–42
25–40
9–16
http://onsemi.com
CFM
70% RPM
18
6160
3080
1540
770
Chassis Intrusion Input
input/open−drain output intended for detection and
signalling of unauthorized tampering with the system. An
external circuit powered from the system’s CMOS backup
battery is used to detect and latch a chassis intrusion event,
whether or not the system is powered up. Once a chassis
intrusion has been detected and latched, the CI input will
generate an interrupt when the system is powered up.
an external circuit that will, for example, detect when the
cover has been removed. A wide variety of techniques may
be used for the detection, for example:
the external detection circuit is reset. This can be achieved
by setting Bit 7 of the Chassis Intrusion Clear Register to
one, which will cause the CI pin to be pulled low for at least
20 ms. This register bit is self−clearing.
can be reset by pulling its output low. A suitable chassis
intrusion circuit using a photo−transistor is shown in
Figure 30. Light falling on the photo−transistor when the PC
cover is removed will cause it to turn on and pull up the input
of 1, thus setting the latch N3/N4. After the cover is
replaced, a low reset on the CI output will pull down the
input of N4, resetting the latch.
BATTERY
The chassis intrusion input is an active high
The actual detection of chassis intrusion is performed by
The chassis intrusion interrupt will remain asserted until
The chassis intrusion circuit should be designed so that it
BACKUP
♦
♦
♦
♦
CMOS
Figure 30. Chassis Intrusion Detector and Latch
removed.
cover.
removed.
Microswitch that opens or closes when the cover is
Reed switch operated by magnet fixed to the cover.
Hall−effect switch operated by magnet fixed to the
Phototransistor that detects light when the cover is
Rev 70% (ms)
Time Per
19.48
38.96
77.92
1N914
9.74
MRD901
470k W
1
2
3
4
5
6
7
60% RPM
5280
2640
1320
660
74HC132
N1
N2
N4
N3
14
13
12
11
10
9
8
Rev 60% (ms)
100kW
11.36
22.73
45.44
90.90
1N914
10kW
5.0 V
CI