STDVE103ABTR STMicroelectronics, STDVE103ABTR Datasheet
STDVE103ABTR
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STDVE103ABTR Summary of contents
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... Front projectors, LCD TVs and PDPs ■ Monitors and notebooks ■ Set-top box and DVD players Table 1. Device summary Order code Operating temperature STDVE103ABTR STDVE103ABTY June 2009 Description : CC The STDVE103A integrates a 4-channel 3.4 Gbps TMDS equalizer and a 3:1 switch to select one the three HDMI ports ...
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Contents Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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STDVE103A 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of tables List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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STDVE103A List of figures Figure 1. STDVE103A block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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General description 1 General description The STDVE103A is a TMDS/HDMI 3:1 switch with signal equalizer. The device is a HDMI switch featuring an integrated 4-channel 3.4 Gbps TMDS equalizer and 3:1 switch to select one of the three HDMI ports ...
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STDVE103A 2 Block diagram Figure 1. STDVE103A block diagram HDMI input port A HDMI input port B HDMI input port C DDC port A DDC port B DDC port C S1,S2 HPD port A HPD port B HPD port C ...
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Block diagram Figure 3. DDC I A_DDC_SDA B_DDC_SDA C_DDC_SDA A_DDC_SCL B_DDC_SCL C_DDC_SCL S1, S2 2.1 Application diagrams Figure 4. STDVE103A in a digital TV 8/ bus repeater Bus Repeater Switch Game DVD-R console Digital TV ...
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STDVE103A 3 Pin configuration Figure 5. Pin configuration (TQFP64 package) 1 SDA 3 2 SCL 3 3 GND 4 B31 A31 5 VCC 6 B32 7 A32 8 GND 9 10 B33 11 A33 12 VCC A34 ...
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Pin configuration Table 2. Pin description (continued) Pin number 16 17-18 19 20-21 22 23-24 25 26- 32- 38-39 40 41-42 43 44-45 46 47- 10/44 Pin name Type ...
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STDVE103A Table 2. Pin description (continued) Pin number 52 53-54 55 56-57 58 59-60 61 62-63 64 Pin name Type SCL2 I/O Port 2 DDC bus clock line B21, A21 Input, TMDS Port 2 differential inputs for channel 1 Power ...
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Functional description 4 Functional description The STDVE103A routes physical layer signals for high bandwidth digital video and is compatible with low voltage differential signaling standards such as the TMDS. The device passes the differential inputs from a video source to ...
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STDVE103A Figure 6. STDVE103A gain vs. frequency The STDVE103A equalizer is fully adaptive and automatic in function. The equalizer’s performance is optimized for all frequencies over the cable lengths from Input termination The STDVE103A integrates ...
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Functional description TMDS voltage levels The TMDS interface standard is a signaling method intended for point-to-point communication over a tightly controlled impedance medium. The TMDS standard uses a lower voltage swing than other common communication standards, achieving higher data rates ...
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STDVE103A 4.2 Operating modes 4.2.1 SEL operating modes The active source is selected by configuring source select inputs, S1 and S2. The selected TMDS inputs from each port are switched through a 3-to-1 multiplexer. The I the selected input port ...
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Functional description 2 4 DDC line repeater The device contains two identical bidirectional open-drain, non-inverting buffer circuits that 2 enable I C DDC bus lines to be extended without degradation in system performance. The STDVE103A buffers both the ...
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STDVE103A 4.7 Bias The bandgap reference voltage over the external R bias reference current. This current and its factors (achieved by employing highly accurate and well matched current mirror circuit topologies) are generated on-chip and used by several internal modules. ...
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Maximum rating 5 Maximum rating Stressing the device above the rating listed in the “absolute maximum ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other ...
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STDVE103A 5.1 Recommended operating conditions 5.2 DC electrical characteristics T = -40 to +85 ° Table 8. Power supply characteristics Symbol Parameter V Supply voltage CC V Supply voltage DD I Supply current CC I Supply current CC ...
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Maximum rating Table 10. DC specifications for TMDS differential outputs Symbol Parameter Single-ended high level V OH output voltage Single-ended low level V OL output voltage Single ended output V swing swing voltage Differential output V voltage OD (1) (peak-to-peak) ...
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STDVE103A Table 11. DC specifications for SEL (S1, S2) inputs Symbol Parameter V HIGH level input voltage IH V LOW level input voltage IL V Clamp diode voltage IK I Input high current IH I Input low current IL C ...
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Maximum rating Table 14. DDC I/O pins (switch) Symbol Parameter V Input voltage I(DDC) I Input leakage current I(leak) C Input/output capacitance I/O Table 15. Status pins (HPD_SINK) Symbol Parameter V High level input voltage IH V Low level input ...
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STDVE103A HPD1, HPD2, HPD3) Table 16. Status pins ( Symbol Parameter V Voltage C Input/output capacitance I/O Output low voltage V OL (open drain I/Os) 1. Typical parameters are measured at V (1) Test condition ...
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Maximum rating 5.3 DC electrical characteristics ( -40 to +85 ° Table 17. Supplies Symbol Parameter V DC supply voltage CC Table 18. Input/output SDA, SCL Symbol Parameter High level input V IH voltage Low level ...
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STDVE103A 5.4 Dynamic switching characteristics T = -40 to +85 ° Typical values are at T Table 19. Clock and data rate Symbol Parameter Clock frequency f (1/10th of the CK differential data rate) D Signaling rate rate ...
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Maximum rating Table 22. Skew times Symbol Parameter Inter-pair channel-to- t SK(O) channel output skew t Pulse skew SK(P) Intra-pair differential t SK(D) skew Output channel to t SK(CC) channel skew Table 23. Turn-on and turn-off times Symbol Parameter TMDS ...
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STDVE103A Table 26. Jitter Symbol Parameter (1) t Total jitter JIT 1. Total jitter is measured peak-to-peak with a histogram including 3500 window hits. Stimulus and fixture jitter has been subtracted. Input differential voltage = V parameter is not production-tested ...
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Maximum rating 5.5 Dynamic switching characteristics ( -40 to +85 ° Typical values are (1) Table 27 repeater Symbol Parameter clock frequency SCL t Low duration ...
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STDVE103A 2 (1) Table 27 repeater (continued) Symbol Parameter t High duration on SCL pin HIGH t High duration on SCL pin HIGH t Propagation delay PHL t Propagation delay PLH t Propagation delay PHL Test condition 100 ...
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Maximum rating 2 (1) Table 27 repeater (continued) Symbol Parameter t Propagation delay PLH t Propagation delay PHL t Propagation delay PLH t Propagation delay PHL t Propagation delay PLH t Output fall time f t Output fall ...
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STDVE103A 2 (1) Table 27 repeater (continued) Symbol Parameter t Output rise time r t Output rise time r 1. All the timing values are tested during characterization and are guaranteed by design and simulation. Not tested in ...
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Maximum rating Figure 7. Test circuit for electrical characteristics Pulse generator load capacitance: include jig and probe capacitance termination resistance; should be equal Figure 8. TMDS output driver TMDS driver ...
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STDVE103A Figure 9. Test circuit for HDMI receiver and driver Ω TMDS TMDS receiver driver = ...
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Maximum rating Figure 10. Test circuit for turn off and turn off times 1.15 V 1.0 V 1.15 V 1.0 V Pulse generator Figure 11. Test circuit for short circuit output current 34/44 V ...
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STDVE103A Figure 12. Propagation delays VA VCM Output Figure 13. Turn-on and turn-off times VCM V ID(p-p) V OD(O) tpLH 80% V OD(p-p) 20% tr SHDN_N 1. OFF V when V ...
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Maximum rating Figure 14. TSK(O) Data In Data Out at Port 0 Data Out at Port 1 Figure 15. TSK(P) Figure 16. TSK(D) 36/44 tpLHX tpHLX 2.5V tpLHY tSK( tpLHy – tpLHx | or | tpHLy – tpHLx ...
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STDVE103A Figure 17. AC waveform 1 (I Figure 18. Test circuit for AC measurements (I 2 Figure 19 bus timing 2 C lines lines) Doc ID 14911 Rev 4 Maximum rating 37/44 ...
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Application information 6 Application information 6.1 Power supply sequencing Proper power-supply sequencing is advised for all CMOS devices recommended to always apply V CC 6.2 Power supply requirements Bypass each of the V device as possible, with the ...
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STDVE103A 2 6.3 lines application information A typical application is shown in the figure below. In the example, the system master is running 100 kHz unless the slave bus is isolated and then ...
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Package mechanical data 7 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available ...
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STDVE103A Table 29. TQFP64 mechanical data Symbol Figure 22. TQFP64 tape and reel information Millimeters Min Typ − − 0.05 0.10 0.95 1 0.17 0.22 ...
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Package mechanical data Figure 23. TQFP64 tray drawing Figure 24. TQPF64 tray drawing dimensions 42/44 Doc ID 14911 Rev 4 STDVE103A ...
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STDVE103A 8 Revision history Table 30. Document revision history Date 21-Jul-2008 09-Sept-2008 27-Mar-2009 01-Jun-2009 Revision 1 Initial release. Changed Table 1: Device summary on page 1 code. Modified the hot-plug detect status in on page 15. 2 Updated ESD information ...
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