PTN3360BBS,518 NXP Semiconductors, PTN3360BBS,518 Datasheet
PTN3360BBS,518
Specifications of PTN3360BBS,518
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PTN3360BBS,518 Summary of contents
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PTN3360B Enhanced performance HDMI/DVI level shifter Rev. 02 — 8 October 2009 1. General description The PTN3360B is a high-speed level shifter device which converts four lanes of low-swing AC-coupled differential input signals to DVI v1.0 and HDMI v1.3a compliant ...
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... NXP Semiconductors MULTI-MODE DISPLAY SOURCE PCIe PHY ELECTRICAL TMDS coded TX data FF TMDS coded TX data FF TMDS coded TX data FF TMDS clock TX pattern FF DDC I CONFIGURATION Remark: TMDS clock and data lanes can be assigned arbitrarily and interchangeably to D[4:1]. Fig 1. Typical application system diagram PTN3360B_2 Product data sheet ...
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... NXP Semiconductors 2. Features 2.1 High-speed TMDS level shifting I Converts four lanes of low-swing AC-coupled differential input signals to DVI v1.0 and HDMI v1.3a compliant open-drain current-steering differential output signals I TMDS level shifting operation up to 2.5 Gbit/s per lane (250 MHz character clock) I Integrated 50 ...
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... NXP Semiconductors 4. Functional diagram Fig 2. PTN3360B_2 Product data sheet OE_N input bias 50 50 IN_D4+ IN_D4 input bias 50 50 IN_D3+ IN_D3 input bias 50 50 IN_D2+ IN_D2 input bias 50 50 IN_D1+ IN_D1 HPD_SOURCE ( 3.3 V) DDC_EN ( 3.3 V) SCL_SOURCE SDA_SOURCE Functional diagram of PTN3360B Rev. 02 — 8 October 2009 ...
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... NXP Semiconductors 5. Pinning information 5.1 Pinning Fig 3. PTN3360B_2 Product data sheet terminal 1 index area GND n.c. n.c. 4 GND 5 6 REXT HPD_SOURCE 7 SDA_SOURCE 8 SCL_SOURCE GND 12 Transparent top view HVQFN48 package supply ground is connected to both GND pins and exposed center pad. GND pins must be connected to supply ground for proper device operation ...
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... NXP Semiconductors 5.2 Pin description Table 2. Pin description Symbol Pin OE_N, IN_Dx and OUT_Dx signals OE_N 25 IN_D4+ 48 IN_D4 47 IN_D3+ 45 IN_D3 44 IN_D2+ 42 IN_D2 41 IN_D1+ 39 IN_D1 38 OUT_D4+ 13 OUT_D4 14 OUT_D3+ 16 OUT_D3 17 OUT_D2+ 19 OUT_D2 20 PTN3360B_2 Product data sheet Type Description 3.3 V low-voltage Output Enable and power saving function for high-speed differential CMOS single-ended level shifter path ...
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... NXP Semiconductors Table 2. Pin description …continued Symbol Pin OUT_D1+ 22 OUT_D1 23 HPD and DDC signals HPD_SINK 30 HPD_SOURCE 7 SCL_SOURCE 9 SDA_SOURCE 8 SCL_SINK 28 SDA_SINK 29 DDC_EN 32 Supply and ground V 2, 11, 15, DD 21, 26, 33, 40 [1] GND 1, 5, 12, 18, 24, 27, 31, 36, 37, 43 Feature control signals REXT 6 Miscellaneous n.c. ...
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... NXP Semiconductors 6. Functional description Refer to The PTN3360B level shifts four lanes of low-swing AC-coupled differential input signals to DVI and HDMI compliant open-drain current-steering differential output signals 2.5 Gbit/s per lane. It has integrated 50 input signals. An enable signal OE_N can be used to turn off the TMDS inputs and outputs, thereby minimizing power consumption. The TMDS outputs, HPD_SINK input and DDC_SINK I/Os are back-power safe to disallow current fl ...
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... NXP Semiconductors 6.1.2 Output Enable function (OE_N) When input OE_N is asserted (active LOW), the IN_Dx and OUT_Dx signals are fully functional. Input termination resistors are enabled and the internal bias circuits are turned on. When OE_N is de-asserted (inactive HIGH), the OUT_Dx outputs are in a high-impedance state and drive zero output current ...
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... NXP Semiconductors 6.1.4 Enable/disable truth table Table 3. HPD_SINK, OE_N and DDC_EN enabling truth table Inputs HPD_SINK OE_N DDC_EN [1] [2] LOW LOW LOW LOW LOW HIGH LOW HIGH LOW LOW HIGH HIGH HIGH LOW LOW HIGH LOW HIGH HIGH HIGH LOW HIGH ...
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... NXP Semiconductors 6.2 Analog current reference The REXT pin (pin analog current sense port used to provide an accurate current reference for the differential outputs OUT_Dx. For best output voltage swing accuracy, use resistor (1 % tolerance) connected between this terminal and GND is recommended external 10 k connected to GND or V value less than 10 k ...
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... NXP Semiconductors 7. Limiting values Table 4. In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol stg V ESD [1] Human Body Model: ANSI/EOS/ESD-S5.1-1994, standard for ESD sensitivity testing, Human Body Model - Component level; Electrostatic Discharge Association, Rome, NY, USA. [2] Charged-Device Model: ANSI/EOS/ESD-S5.3-1-1999, standard for ESD sensitivity testing, Charged-Device Model - Component level ...
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... NXP Semiconductors 9. Characteristics 9.1 Differential inputs Table 7. Differential input characteristics for IN_Dx signals Symbol Parameter [1] UI unit interval V differential input peak-to-peak voltage RX_DIFFp-p T receiver eye time RX_EYE V peak common-mode input voltage (AC) i(cm)M(AC input impedance RX_DC V bias receiver voltage RX(bias) Z single-ended input impedance ...
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... NXP Semiconductors 9.2 Differential outputs The level shifter’s differential outputs are designed to meet HDMI version 1.3 and DVI version 1.0 specifications. Table 8. Differential output characteristics for OUT_Dx signals Symbol Parameter V single-ended HIGH-level OH(se) output voltage V single-ended LOW-level OL(se) output voltage ...
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... NXP Semiconductors 9.4 OE_N, DDC_EN inputs Table 10. OE_N, DDC_EN and DDET input characteristics Symbol Parameter V HIGH-level input voltage IH V LOW-level input voltage IL I input leakage current LI [1] Measured with input at V maximum and V IH 9.5 DDC characteristics Table 11. DDC characteristics Symbol ...
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... NXP Semiconductors 10. Package outline HVQFN48: plastic thermal enhanced very thin quad flat package; no leads; 48 terminals; body 0.85 mm terminal 1 index area terminal 1 48 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... NXP Semiconductors 11. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 11.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...
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... NXP Semiconductors 11.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...
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... NXP Semiconductors Fig 5. For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 12. Abbreviations Table 14. Acronym CDM DDC DVI ESD HBM HDMI HPD 2 I C-bus I/O TMDS PTN3360B_2 Product data sheet maximum peak temperature = MSL limit, damage level ...
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... NXP Semiconductors 13. Revision history Table 15. Revision history Document ID Release date PTN3360B_2 20091008 • Modifications: Section 6 “Functional rd – – 5 paragraph, 2 • Table 7 “Differential input characteristics for IN_Dx OE_N is LOW.” to “... when OE_N is HIGH.” • Table 8 “Differential output characteristics for OUT_Dx ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 16. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1 High-speed TMDS level shifting . . . . . . . . . . . . 3 2.2 DDC level shifting . . . . . . . . . . . . . . . . . . . . . . . 3 2.3 HPD level shifting . . . . . . . . . . . . . . . . . . . . . . . 3 2.4 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 4 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 Functional description . . . . . . . . . . . . . . . . . . . 8 6.1 Enable and disable features . . . . . . . . . . . . . . . 8 6 ...