AD9895KBCRL Analog Devices Inc, AD9895KBCRL Datasheet - Page 37

• Manufacturer Part Number: AD9895KBCRL
• Description: IC CCD SIGNAL PROC/GEN 64-CSPBGA
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 12-Bitr

Specifications of AD9895KBCRL

• Rohs Status: RoHS non-compliant
• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Mounting Type: Surface Mount
• Package / Case: 64-CSPBGA
• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Sample Rate: 30MSPS
• Operating Supply Voltage (min): 2.7/3V
• Resolution: 12b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: CSPBGA
• Number Of Channels: 1
• Current - Supply: -
• Lead Free Status / RoHS Status: Not Compliant

HORIZONTAL TIMING SEQUENCE EXAMPLE
Figure 45 shows an example CCD layout. The horizontal regis-
ter contains 28 dummy pixels that will occur on each line
clocked from the CCD. In the vertical direction, there are 10
optical black (OB) lines at the front of the readout and two at
the back of the readout. The horizontal direction has four OB
pixels in the front and 48 in the back.
To configure the AD9891/AD9895 horizontal signals for this
CCD, three sequences can be used. Figure 46 shows the first
sequence to be used during vertical blanking. During this time,
there are no valid OB pixels from the sensor, so the CLPOB and
REV. A
CLPDM PULSE MAY BE USED DURING HORIZONTAL DUMMY PIXELS IF THE H-CLOCKS ARE USED DURING VERTICAL BLANKING.
CLPDM
CLPOB
CCDIN
H1/H3
H2/H4
HBLK
PBLK
SHP
SHD
SEQUENCE 1: VERTICAL BLANKING
INVALID PIX
28 DUMMY PIXELS
VERTICAL SHIFT
4 OB PIXELS
V
Figure 46. Horizontal Sequences During Vertical Blanking
EFFECTIVE IMAGE AREA
HORIZONTAL CCD REGISTER
Figure 45. Example CCD Configuration
DUMMY
H
48 OB PIXELS
–37–
CLPDM signals are not used. In some cases, if the horizontal
clocks are used during this time, the CLPDM signal may be used
to keep the AD9891/AD9895’s input clamp partially settled.
PBLK may be enabled during this time because no valid data is
available.
Figure 47 shows the recommended sequence for the vertical OB
interval. The clamp signals are used across the whole lines in
order to stabilize the clamp loops of the AD9891/AD9895.
Figure 48 shows the recommended sequence for the effective
pixel readout. The 48 OB pixels at the end of each line are used
for the CLPOB and CLPDM signals.
10 VERTICAL OB LINES
2 VERTICAL OB LINES
INVALID PIXELS
USE SEQUENCE 3
USE SEQUENCE 2
SEQUENCE 2 (OPTIONAL)
AD9891/AD9895
VERT SHIFT