AD9895KBCRL Analog Devices Inc, AD9895KBCRL Datasheet - Page 14
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AD9895KBCRL
Manufacturer Part Number
AD9895KBCRL
Description
IC CCD SIGNAL PROC/GEN 64-CSPBGA
Manufacturer
Analog Devices Inc
Type
CCD Signal Processor, 12-Bitr
Datasheet
1.AD9895KBCZRL.pdf
(58 pages)
Specifications of AD9895KBCRL
Rohs Status
RoHS non-compliant
Input Type
Logic
Output Type
Logic
Interface
3-Wire Serial
Mounting Type
Surface Mount
Package / Case
64-CSPBGA
Analog Front End Type
CCD
Analog Front End Category
Video
Interface Type
Serial (3-Wire)
Sample Rate
30MSPS
Operating Supply Voltage (min)
2.7/3V
Resolution
12b
Number Of Adc's
1
Power Supply Type
Analog/Digital
Operating Temp Range
-20C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
64
Package Type
CSPBGA
Number Of Channels
1
Current - Supply
-
Lead Free Status / RoHS Status
Not Compliant
AD9891/AD9895
POSITION
PERIOD
SIGNAL
NOTES
ALL SIGNAL EDGES ARE FULLY PROGRAMMABLE TO ANY OF THE 48 POSITIONS WITHIN ONE PIXEL PERIOD.
DEFAULT POSITIONS FOR EACH SIGNAL ARE SHOWN.
PIXEL
H1/H3
CCD
RG
H1/H3
H2/H4
PERIOD
PIXEL
DCLK
DOUT
NOTES
DATA OUTPUT (DOUT) AND DCLK PHASE ARE ADJUSTABLE WITH RESPECT TO THE PIXEL PERIOD.
WITHIN 1 CLOCK PERIOD, THE DATA TRANSITION CAN BE PROGRAMMED TO 48 DIFFERENT LOCATIONS.
OUTPUT DELAY (
Figure 10. High Speed Clock Default and Programmable Locations
P[0]
P[0]
RGr[0]
Hr[0]
t
t
RISE
OD
) FROM DCLK RISING EDGE TO DOUT RISING EDGE IS PROGRAMMABLE.
t
OD
Figure 11. H-Clock Inverse Phase Relationship
Figure 12. Digital Output Phase Adjustment
FIXED CROSSOVER VOLTAGE
RGf[12]
P[12]
P[12]
t
PD
–14–
<
P[24]
P[24]
Hf[24]
t
RISE
SHP[28]
H1/H3
P[36]
P[36]
t
S1
t
PD
P[48] = P[0]
P[48] = P[0]
SHD[48]
H2/H4
REV. A