CP2120-GM Silicon Laboratories Inc, CP2120-GM Datasheet - Page 11

IC I/O EXPANDER I2C/SPI 8B 20QFN

CP2120-GM

Manufacturer Part Number
CP2120-GM
Description
IC I/O EXPANDER I2C/SPI 8B 20QFN
Manufacturer
Silicon Laboratories Inc
Type
SPI to I2C Bridger
Datasheets

Specifications of CP2120-GM

Package / Case
20-QFN
Interface
I²C, SPI
Number Of I /o
8
Interrupt Output
Yes
Frequency - Clock
400kHz
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 55 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
336-1324

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CP2120-GM
Manufacturer:
AMS
Quantity:
195
Part Number:
CP2120-GMR
Manufacturer:
PANASONIC
Quantity:
12 500
5.2.2. Read From Internal Register
A Read from Internal Register command retrieves the current value of one of the CP2120's internal registers. The
command begins with the command byte, 0x21, followed by the internal register address. This byte is followed by
the transmission of a "don't care" byte, which can be of any value and is ignored by the CP2120. After the "don't
care" byte, the internal register value is transmitted across the MISO line.
5.3. SPI Byte Orientation
The SPI Configuration command configures the bit orientation of transfers across the SPI bus to one of two states.
If SPI transmits most-significant-bit first, bit 7 is transmitted first. If SPI transmits least-significant-bit first, bit 0 is
transmitted first.
5.3.1. SPI Configuration
The command begins with the command byte (0x18), followed by SPI Configuration byte, which should equal one
of the values shown in the following table. Any values other than those listed in the table are ignored.
5.4. SPI Timing Diagrams
SCK*
MISO
MOSI
T
NSS
SEZ
SPI Master
CP2120
T
SE
SPI Master
COMMAND
T
CKH
T
0x21
SOH
T
Byte Value
SIS
0x81
0x42
COMMAND
Figure 4. SPI Slave Timing
T
CKL
0x18
T
REGISTER
SIH
Address
Rev. 0.4
Least Significant Bit First
Most Significant Bit First
Configuration
CONFIGURATION
Don’t Care
SPI
T
REGISTER
SLH
DATA
T
SD
CP2120
T
SDZ
11

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