PCA9501D,112 NXP Semiconductors, PCA9501D,112 Datasheet - Page 8

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PCA9501D,112

Manufacturer Part Number
PCA9501D,112
Description
IC I/O EXPANDER I2C 8B 20SOIC
Manufacturer
NXP Semiconductors
Datasheet

Specifications of PCA9501D,112

Interface
I²C, SMBus
Number Of I /o
8
Interrupt Output
Yes
Frequency - Clock
400kHz
Voltage - Supply
2.5 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
20-SOIC (7.5mm Width)
Includes
EEPROM
For Use With
OM6285 - EVAL BOARD I2C-2002-1A568-4002 - DEMO BOARD I2C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
568-3353-5
935272364112
PCA9501D
NXP Semiconductors
PCA9501_4
Product data sheet
7.4.1.1 Byte write
7.4.1 Write operations
7.4 Memory operations
Write operations require an additional address field to indicate the memory address
location to be written. The address field is eight bits long providing access to any one of
the 256 words of memory. There are two types of write operations, ‘byte write’ and ‘page
write’.
Write operation is possible when the Write Control pin (WC) is put at a LOW logic level (0).
When this control signal is set at 1, write operation is not possible and data in the memory
is protected.
‘Byte write’ and ‘page write’ explained below assume that WC is set to 0.
To perform a byte write, the START condition is followed by the memory slave address and
the R/W bit set to 0. The PCA9501 will respond with an acknowledge and then consider
the next eight bits sent as the word address and the eight bits after the word address as
the data. The PCA9501 will issue an acknowledge after the receipt of both the word
address and the data. To terminate the data transfer the master issues the STOP
condition, initiating the internal write cycle to the non-volatile memory. Only write and read
operations to the quasi-bidirectional I/Os are allowed during the internal write cycle.
Fig 10. Application of multiple PCA9501s with interrupt
Fig 11. Interrupt generated by a change of input to IO5
data into IO5
MICROCONTROLLER
INT
SDA
INT
SCL
Rev. 04 — 10 February 2009
8-bit I
t
v(INT)
S
START condition
slave address (I/O expander)
1
0
2
V
C-bus and SMBus I/O port with interrupt, 2-kbit EEPROM
2
A5 A4 A3 A2 A1 A0
DD
3
4
PCA9501
device 1
5
INT
6
t
rst(INT)
7
R/W
8
1
PCA9501
9
A
device 2
acknowledge
from slave
INT
IO5
data from port
1
PCA9501
© NXP B.V. 2009. All rights reserved.
PCA9501
device 16
1
002aad293
INT
002aad294
P
STOP
condition
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