CAT9555WI-T1 ON Semiconductor, CAT9555WI-T1 Datasheet - Page 12

• Manufacturer Part Number: CAT9555WI-T1
• Description: IC I/O EXPANDER I2C 16B 24SOIC
• Manufacturer: ON Semiconductor

Specifications of CAT9555WI-T1

• Interface: I²C, Serial, SMBus
• Number Of I /o: 16
• Interrupt Output: Yes
• Frequency - Clock: 400kHz
• Voltage - Supply: 2.3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (7.5mm Width)
• Includes: POR
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 9555WI-T2; CAT9555WI-T1TR; CAT9555WI-T2; CAT9555WI-T2TR; CAT9555WI-T2TR

CAT9555
Power-On Reset Operation
When the power supply is applied to V
internal power-on reset pulse holds the CAT9555 in a
reset state until V
Doc. No. MD-9003 Rev. J
Note:
S
READFROMPORT 0
DATA INTO POR T 0
READFROMPORT 1
DATA INTO POR T 1
Note: Transfer can be stopped at any time by a STOP condition.
SDA
SCL
INT
0
1
S
Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode).
It is assumed that the command byte has previously been set to 00 (read input port register).
slave address
1
0
0
2
1
0
3
0
t
A2 A1 A0
IV
4
0
CC
A2
5 6
A1
reaches V
DATA 00
acknowledge
from slave
R/W
7
A0
0
R/W ACKNOWLEDGE
8
1
A
A
9
FROMSLAVE
DATA 10
POR
t
t
IR
ph
level. At this point,
DATA 00
COMMAND BYTE
DATA 01
I0.x
Figure 11. Read Input Port Register
Figure 10. Read from Register
CC
pin, an
A
ACKNOWLEDGE
FROMMASTER
acknowledge
from slave
at this moment master-transmitter
becomes master-receiver and
slave-receiver becomes
slave-transmitter
t
ph
A
12
DATA 10
DATA 02
S
DATA 11
I1.x
the reset condition is released and the internal state
machine and the CAT9555 registers are initialized to
their default state.
0
0
slave address
1
A
0
ACKNOWLEDGE
FROM MASTER
t
ps
A2 A1 A0
DATA 03
DATA 03
acknowledge
from slave
I0.x
R/W
1
MSB
A
Characteristics subject to change without notice
MSB
data from upper
or lower byte of
A
register
ACKNOWLEDGE
FROM MASTER
last byte
data from lower
t
DATA
ps
or upper byte
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of register
first byte
DATA 12
DAT A
DATA 12
I1.x
LSB
no acknowledge
NON ACKNOWLEDGE
from master
FROM MASTER
acknowledge
from master
NA
LSB
P
1
A
P