HSP43220JC-25Z Intersil, HSP43220JC-25Z Datasheet - Page 12

• Manufacturer Part Number: HSP43220JC-25Z
• Description: IC DECIMATING DGTL FILTER 84PLCC
• Manufacturer: Intersil

Specifications of HSP43220JC-25Z

• Filter Type: Digital
• Number Of Filters: 4
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Package / Case: 84-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Frequency - Cutoff Or Center: -
• Max-order: -

FOR: OUT_SELH = 1, F_BYP = 0
FOR: OUT_SELH = 0, F_BYP = 0
FOR: OUT_SELH = X, F_BYP = 1
Operational Section
Start Configurations
The scenario to put the DDF into operational mode is: reset
the DDF by asserting the RESET input, configure the DDF
over the control bus, and apply a start signal, either by
ASTARTIN or STARTIN. Until the DDF is put in operational
mode with a start pulse, the DDF ignores all data inputs.
To use the asynchronous start, an asynchronous active low
pulse is applied to the ASTARTIN input. ASTARTIN is
internally synchronized to the sample clock, CK_IN, and
generates STARTOUT. This signal is also used internally
2
-2
-2
23
23
15
-16
8
0
2
.
22
2
22
-17
14
2
7
-1
2
21
2
21
-2
-18
19
2
13
6
-2
0
.
2
20
2
20
-19
18
2
2
12
5
-1
-3
OUT_SELH
2
19
2
19
-20
2
F_BYP
17
4
2
OUT_ENX
OUT_SELH = 1
11
-2
-2
-4
15
0
2
18
2
18
F_BYP = 0
-21
2
.
16
3
2
10
12
-3
-5
14
2
-1
2
2
17
2
17
8
-22
2
2
- 2
15
2
DATA_OUT16-23
-4
9
2
13
-6
1
-2
2
16
2
16
-23
1
2
8
14
2
MUX
-5
2
8
12
-7
-3
8
8
2
13
2
2
-6
2
15
7
15
11
2
-8
-16
-4
FIGURE 10. FIR OUTPUT FORMATTER
0
2
F_BYP = 0
OUT_SELH = 0
-16
FIR COEFFICIENT FORMAT
Fractional Two's Complement Output
2
Fractional Two's Complement Input
Fractional Two's Complement Input
12
F_BYP = 1
.
2
-7
2
OUTPUT DATA FORMAT
2
10
14
6
14
-9
- 2
-17
2
INPUT DATA FORMAT
-5
-1
OR
-23
2
11
2
-8
2
2
2
-10
13
5
13
9
-18
-6
-2
HSP43220
2
FIGURE 11.
10
2
-9
2
2
2
-11
12
4
12
8
-19
-7
-3
2
-10
2
9
2
2
2
-12
3
11
11
7
-20
-8
-4
40
when the asynchronous mode is selected. It puts the DDF in
operational mode and allows the DDF to begin accepting
data. When the ASTARTIN input is being used, the STARTIN
input must be tied high to ensure proper operation.
To start the DDF synchronously, the STARTIN is asserted
with a active low pulse that has been externally
synchronized to CK_IN. Internally the DDF then uses this
start pulse to put the DDF in operate mode and start
accepting data inputs. When STARTIN is used to start the
DDF the ASTARTIN input must be tied high to prevent false
starts.
2
-11
8
2
2
2
2
-13
2
6
10
10
-9
-21
-5
2
-12
7
2
2
F_BYP = 0
2
-10
2
-14
1
5
-22
9
9
2
-6
0
2
- 2
-13
6
2
2
2
-11
2
-15
-15
4
0
-23
8
8
-7
DATA_OUT0 -15
2
-14
5
2
2
-12
16 16
2
3
-24
7
7
MUX
-8
2
2
23
-16
-15
16
4
2
2
-13
2
2
-25
6
6
-9
2
22
-17
2
F_BYP = 1
2
-16
2
2
-14
1
2
-10
-26
5
5
-16
3
2
- 2
21
OUT_ENP
-18
2
-31
2
-15
2
0
2
-11
-27
4
4
F_BYP
2
-17
2
20
-19
2
2
2
-12
2
-28
3
3
-18
1
19
-20
2
2
2
2
-13
-29
2
2
-19
0
18
-21
October 10, 2008
2
2
2
-14
-30
1
17
1
-22
FN2486.10
2
2
2
16
-15
-31
0
-23
0