HSP43220JC-25Z Intersil, HSP43220JC-25Z Datasheet - Page 11

• Manufacturer Part Number: HSP43220JC-25Z
• Description: IC DECIMATING DGTL FILTER 84PLCC
• Manufacturer: Intersil

Specifications of HSP43220JC-25Z

• Filter Type: Digital
• Number Of Filters: 4
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Package / Case: 84-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Frequency - Cutoff Or Center: -
• Max-order: -

FIR Output
The 40 most significant bits of the accumulator are latched
into the output register. The lower 3 bits are not brought to
the output. The 40 bits out of the output register are selected
to be output by a pair of multiplexers. This register is clocked
by FIR_CK (see Figure 9).
There are two multiplexers that route 24 of the 40 output bits
from the output register to the output pins. The first
multiplexer selects the output register bits that will be routed
to output pins DATA_OUT16-23 and the second multiplexer
selects the output register bits that will be routed to output
pins DATA_OUT0-15.
The multiplexers are controlled by the control signal F_BYP
and the OUT_SELH pin. F_BYP and OUT_SELH both
F_DRATE
FROM COEFFICIENT
FIR_CK
FROM CONTROL REGISTERS
F_TAPS
FORMATTER
FIR CONTROL LOGIC
FROM HDF
DATA_RDY
REG
11
F_BYP
20
16
COEFFICIENT
16 x 512
20 x 256
F_DIS
DATA
RAM
RAM
FIGURE 9. FIR FILTER
HSP43220
MULTIPLIER/
ACCUMULATOR
SECTION
DATA_RDY
16
16
20
FIR_CK
control the first multiplexer that selects the upper 8 bits of
the output bus, DATA_OUT16-23. F_BYP controls the
second multiplexer that selects the lower 16 bits of the
output bus, DATA_OUT0-15. The output formatter is shown
in detail in Figure 10.
FIR Control Logic
The DATA_RDY strobe indicates that new data is available on
the output of the FIR. The rising edge of DATA_RDY can be
used to load the output data into an external register or RAM.
Data Format
The DDF maintains 16 bits of accuracy in both the HDF and
FIR filter stages. The data formats and bit weightings are
shown in Figure 11.
F_CLA
F_OAD
F_CLA
MUX
REG
REG
17 x 20 BIT MULTIPLIER ARRAY
REG
20
43-BIT ACCUMULATOR
PRE-ADDER LOGIC
DATA_OUT 0 -23
16
16
OUTPUT REG
FORMATTER
OUTPUT
REG
37
37
PRE-ADDER
43
40
24
F_ESYM
REG
17
17
17
43
October 10, 2008
REG
FN2486.10