STA016AP STMicroelectronics, STA016AP Datasheet - Page 17

• Manufacturer Part Number: STA016AP
• Description: DECODER AUDIO MPEG 2.5 64-TQFP
• Manufacturer: STMicroelectronics
• Type: Audio Decoderr

Specifications of STA016AP

• Applications: Multimedia
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply, Analog: -
• Voltage - Supply, Digital: -

Description :
This register must contain a XDIV value that enables
the system PLL to generate a frequency of 50 MHZ
for the SYSCK. See table 4.
Default value at soft reset assume :
6.3.5
Address : 0xEA (234)
Type : RW - DEC
Software Reset : 13
Description :
This register must contain a MDIV value that enables
the system PLL to generate a frequency of 50 MHz
for the SYSCK. See table 4.
Default value at soft reset assume :
6.3.6
Address : 0xE6 (230)
Type : RW - DEC
Software Reset : 126
Description :
This register must contain a PEL value that enables
the system PLL to generate a frequency of 42.5 MHz
for the SYSCK.See table 4.
Default value at soft reset assume :
6.3.7
Address : 0xE7 (231)
Type : RW - DEC
Software Reset : 223
b7
b7
b7
– external crystal provide a CRYCK running at
– external crystal provide a CRYCK running at
– external crystal provide a CRYCK running at
14.31818 MHz
14.31818 MHz
14.31818 MHz
PLL_SYSTEM_MDIV_50 :
PLL_SYSTEM_PEL_42_5
PLL_SYSTEM_PEH_42_5 :
b6
b6
b6
b5
b5
b5
b4
b4
b4
b3
b3
b3
b2
b2
b2
b1
b1
b1
b0
b0
b0
Description :
This register must contain a PEH value that enables
the system PLL to generate a frequency of 42.5 MHz
for the SYSCK.See table 4.
Default value at soft reset assume :
6.3.8
6.3.9
Address : 0xE8 (232)
Type : RW - DEC
Software Reset : 0
Description :
This register must contain a NDIV value that enables
the system PLL to generate a frequency of 42.5 MHz
for the SYSCK.See table 4.
Default value at soft reset assume :
6.3.10 PLL_SYSTEM_XDIV_42_5 :
Address : 0xE9 (233)
Type : RW - DEC
Software Reset : 1
Description :
This register must contain a XDIV value that enables
the system PLL to generate a frequency of 42.5 MHz
for the SYSCK.See table 4.
Default value at soft reset assume :
6.3.11 PLL_SYSTEM_MDIV_42_5 :
Address : 0xEA (234)
b7
b7
b7
– external crystal provide a CRYCK running at
– external crystal provide a CRYCK running at
– external crystal provide a CRYCK running at
14.31818 MHz
14.31818 MHz
14.31818 MHz
PLL_SYSTEM_NDIV_42_5 :
b6
b6
b6
b5
b5
b5
b4
b4
b4
b3
b3
b3
b2
b2
b2
STA016A
b1
b1
b1
17/43
b0
b0
b0