CS493105-CLZ Cirrus Logic Inc, CS493105-CLZ Datasheet - Page 72

• Manufacturer Part Number: CS493105-CLZ
• Description: IC DECODER AUD MULTI STD 44PLCC
• Manufacturer: Cirrus Logic Inc
• Type: Audio Decoderr

Specifications of CS493105-CLZ

• Applications: DVD
• Voltage - Supply, Analog: 2.37 V ~ 2.63 V
• Voltage - Supply, Digital: 2.37 V ~ 2.63 V
• Mounting Type: Surface Mount
• Package / Case: 44-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 598-1670

10.5. Digital Audio Output Port
The Digital Audio Output port, or DAO, is the port
used for digital output from the DSP.
shows the signals associated with the DAO. As
with the input ports the clocks and data are fully
configurable via hardware configuration.
MCLK is the master clock and is firmware
configurable to be either an input or an output. If
MCLK is to be used as an output, the internal PLL
must be used. As an output MCLK can be
configured to provide a 128Fs, 256Fs or 512Fs
clock, where Fs is the output sample rate.
SCLK is the bit clock used to clock data out on
AUDATA0, AUDATA1, AUDATA2 and AUDATA3.
LRCLK is the data framing clock whose frequency
is typically equal to the sampling frequency. Both
LRCLK and SCLK can be configured as either
inputs (Slave mode) or outputs (Master mode).
When LRCLK and SCLK are configured as inputs,
MCLK is a don’t care as an input. When LRCLK
and SCLK are configured as outputs, they are
derived from MCLK. Whether MCLK is configured
as an input or an output, an internal divider from
the MCLK signal is used to produce LRCLK and
SCLK. The ratios shown in
possible
72
AUDATA3,
XMT958
AUDATA2
AUDATA1
AUDATA0
LRCLK
SCLK
MCLK
Pin Name
Table 15. Digital Audio Output Port
SCLK
IEC60958 Transmitter
Pin Description
Serial Data Out
Serial Data Out
Serial Data Out
Serial Data Out
Serial Bit Clock
Master Clock
Frame Clock
values
for
Table 16
different
Pin Number
Table 15
give the
39
40
41
42
43
44
3
MCLK
frequencies (all values in terms of the sampling
frequency, Fs).
** For MCLK as an input only
AUDAT0 is configurable to provide six, four, or two
channels. AUDATA1, AUDATA2 and AUDATA3
can both output two channels of data. Typically the
AUDATA0, AUDATA1, AUDATA2 and AUDATA3
outputs are used in left justified, I2S or right
justified
AUDATA2 are used for 5.1 output, presenting all
six channels of surround sound (Left, Center,
Right,
Subwoofer).
AUDATA3 can be used with AUDATA0, AUDATA1
and AUDATA2 to support 7.1 output. Alternatively
AUDATA3 can be used for dual zone support.
AUDATA3 is multiplexed with the XMT958 output
so only one can be used at any one time.
Table 17
actual outputs when not in a multichannel mode.
128
384**
256
512
MCLK
DAO_Channel
(Fs)
Table 16. MCLK/SCLK Master Mode Ratios
0
1
2
3
4
5
6
7
Table 17. Output Channel Mapping
Left
shows the mapping of DAO channels to
modes.
32
X
X
X
X
Surround,
48
CS49300 Family DSP
X
Subframe
AUDATA0,
Right
Right
Right
Right
Left
Left
Left
Left
SCLK (Fs)
64
X
X
X
X
Right
128
X
X
AUDATA1
Surround
AUDATA0
AUDATA0
AUDATA1
AUDATA1
AUDATA2
AUDATA2
AUDATA3
AUDATA3
256
Signal
X
X
DS339F7
512
X
and
and