CS493105-CLZ Cirrus Logic Inc, CS493105-CLZ Datasheet - Page 51

• Manufacturer Part Number: CS493105-CLZ
• Description: IC DECODER AUD MULTI STD 44PLCC
• Manufacturer: Cirrus Logic Inc
• Type: Audio Decoderr

Specifications of CS493105-CLZ

• Applications: DVD
• Voltage - Supply, Analog: 2.37 V ~ 2.63 V
• Voltage - Supply, Digital: 2.37 V ~ 2.63 V
• Mounting Type: Surface Mount
• Package / Case: 44-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 598-1670

7.
If using one of the serial modes, i.e. SPI or I
system designer has the option of using external
memory. The external memory interface is not
compatible with the parallel modes since there are
shared pins that are needed by each mode.
The external memory interface was designed for
autoboot and to extend the data memory range of
the DSP during runtime. The application user’s
guide for a particular code load will inform the
system designer if memory is required. If no
mention is made of external memory, then external
memory is not required for that application.
The external memory interface is implemented on
the
EMAD[7:0], EXTMEM, EMOE, and EMWR.
Table 8
pin number of each signal on the CS493XX.
EMAD[7:0] serve as a multiplexed address and
data bus. EMOE is an active-low external-memory
data output enable as well as the address latch
strobe. EMWR is an active low write enable.
EXTMEM serves as the active low chip select
output.
* - These pins must be configured appropriately to
select a serial host communication mode for the
CS493XX at the rising edge of RESET
Figure 30, "External Memory Interface" on page 53
illustrates
architecture for the CS493XX.
Memory Read (16-bit address)" on page 53
the functional timing of a 16 bit address memory
read and
DS339F7
/EMOE
/EMWR
/EXTMEM
EMAD7
EMAD6
EMAD5
EMAD4
EMAD3
EMAD2
EMAD1
EMAD0
Pin Name
EXTERNAL MEMORY
CS493XX
shows the pin name, pin description and
Table 8. Memory Interface Pins
Figure 32, "External Memory Write (16-
* External Memory Output Enable
* External Memory Write Strobe
one
External Memory Select
& Address Latch Strobe
Address and Data Bit 7
Address and Data Bit 6
Address and Data Bit 5
Address and Data Bit 4
Address and Data Bit 3
Address and Data Bit 2
Address and Data Bit 1
Address and Data Bit 0
with
Pin Description
possible
the
Figure 31, "External
external
following
Number
memory
signals:
2
Pin
shows
21
10
14
15
16
17
11
C, the
5
4
8
9
bit address)" on page 53
timing of a 16 bit address memory write. It should
be noted that this memory example gives the DSP
visibility to up to 64 kilobytes of memory.
The external memory address is capable of
addressing up to 16 megabytes total through a 24
bit addressing scheme. The address comes from
the DSP writing three initial bytes of address
consecutively on EMAD[7:0]. Each byte of address
is externally latched with the rising edge of EMOE
while EXTMEM is high. After the 3-byte address is
latched externally, the CS493XX then drives
EXTMEM and EMOE low simultaneously to select
the external memory. During this time the data is
read by the CS493XX.
To extend the example shown in Figures
to allow for a 24-bit address, the system designer
would add another latch to the system. The DSP
always places the most significant address bits first
(see Figures 30, 31, and
It should be noted that there are currently no
applications for the CS493XX that use more than
32 kilobytes of external memory (RAM or ROM),
which corresponds to only 15 address lines.
7.1. Non-Paged Memory
Non-paged memories can be used for autobooting
a single piece of full download application code
such as MP3, HDCD, or SRS Circle Surround. A
non-paged memory architecture should be used in
systems which will need to access a single dsp
application code image (32 Kilobyte maximum),
which means that only 15 bits would be required to
access the entire application code image. The 16th
address bit coming from the DSP should be left
unconnected. Figure 35 shows the functional
timing of an autoboot sequence in which three
address cycles are illustrated.
The DSP always considers its address space to
range from 0x0000 to 0xFFFF. This means that the
decoder is unaware of any data which falls outside
of this 64 Kilobyte range. When the DSP is
performing an autoboot, the process always
begins with address 0x0000. This means that the
host microcontroller must be involved in memory
accesses which exceed the 32 Kilobyte scope of
the CS493XX, and the host must also manage
access to all pieces of autoboot code which do not
CS49300 Family DSP
32
shows the functional
for details).
30
to
32
51