CS493105-CLZ Cirrus Logic Inc, CS493105-CLZ Datasheet - Page 57

• Manufacturer Part Number: CS493105-CLZ
• Description: IC DECODER AUD MULTI STD 44PLCC
• Manufacturer: Cirrus Logic Inc
• Type: Audio Decoderr

Specifications of CS493105-CLZ

• Applications: DVD
• Voltage - Supply, Analog: 2.37 V ~ 2.63 V
• Voltage - Supply, Digital: 2.37 V ~ 2.63 V
• Mounting Type: Surface Mount
• Package / Case: 44-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 598-1670

5) After receiving the BOOT_START byte, the
6) The end of the .LD file contains a three byte
7) After reading out the BOOT_SUCCESS byte,
8) After waiting 5ms to allow the downloaded
8.1.2. Parallel Download Sequence
The following is a detailed description of a parallel
download sequence for the CS493XX.
1) A download sequence is started when the host
2) The host should then send the boot message
3) If
4) If initialization fails, the CS493XX sends out an
DS339F7
waiting for a hard reset. The host should re-try
steps 1 through 3 and if failure is met again, the
serial communication timing and protocol
should be inspected.
host should write the downloadable image
(from the .LD file).
checksum. If the checksum is good after
download,
BOOT_SUCCESS message (0x02) to the
host. If the checksum was bad, the CS493XX
responds with the BAD_CHECKSUM message
byte (0xFF) and spins, waiting for hard reset.
the
BOOT_SUCCESS_RECEIVED
(0x000005) which will cause an internal
application
downloaded application to run.
application to initialize, the host can send
configuration messages for both hardware and
software configuration.
issues a hard reset and holds the mode pins
appropriately (WR, RD, and PSEL).
DOWNLOAD_BOOT (0x000004). This causes
the CS493XX to initialize itself for download.
CS493XX sends out the boot message
BOOT_START (0x01) and the host should
proceed to step 5.
INIT_FAILURE boot message byte (0xFD or
0xFE),
BOOT_ERROR byte (0xFA or 0xFC) and spins
waiting for a hard reset. The host should re-try
Note: When reading from the chip in a parallel
communication mode, the host must read the
HOSTCTL register and test the HOUTRDY bit
before starting the read cycle.
the
host
initialization
INVALID_MSG
the
code
CS493XX
should
reset
was
byte
and
successful
will
send
(0xFB),
allow
message
send
the
the
the
or
a
5) After receiving the BOOT_START byte, the
6) The end of the .LD file contains a three byte
7) After reading out the BOOT_SUCCESS byte,
8) After waiting 5ms to allow the downloaded
8.2. Autoboot
Autoboot is a feature available on all DSPs in the
CS493XX family which gives the decoder the
ability to load application code into itself from an
external memory. Because external memory is
accessed through the external memory interface,
autoboot restricts the host control modes to serial
communication (I
external memory interface shown in
"External Memory Interface" on page 53
referenced.
RESET and ABOOT are the control pins which are
used to initiate an autoboot operation by the host
controller. It is important to be aware that the
ABOOT pin also serves as the INTREQ pin, which
means that it will be driven by the CS493XX when
not in reset. Due to this constraint, ABOOT should
be connected to an open-drain output of the
microcontroller so as to allow the specified pull-up
resistor to generate a logic high level. At the
completion of a successful download, INTREQ
(ABOOT) becomes an output and the host should
no longer drive it.
steps 1 through 3 and if failure is met again, the
serial communication timing and protocol
should be inspected.
host should write the downloadable image
(from the .LD file).
checksum. If the checksum is good after
download,
BOOT_SUCCESS message (0x02) to the
host. If the checksum was bad, the CS493XX
responds with the BAD_CHECKSUM message
byte (0xFF) and spins, waiting for hard reset.
the
BOOT_SUCCESS_RECEIVED
(0x000005) which will cause an internal
application
downloaded application to run.
application to initialize, the host can send
configuration messages for both hardware and
software configuration.
host
the
code
CS49300 Family DSP
2
C or SPI). For this section the
CS493XX
should
reset
and
will
send
allow
Figure 30,
message
send
can be
the
the
57
a