SAA7105E/V1/G,518 NXP Semiconductors, SAA7105E/V1/G,518 Datasheet - Page 47

• Manufacturer Part Number: SAA7105E/V1/G,518
• Description: IC DIGITAL VIDEO ENCODER 156LBGA
• Manufacturer: NXP Semiconductors
• Type: Video Encoderr

Specifications of SAA7105E/V1/G,518

• Applications: TV
• Voltage - Supply, Analog: 3.15 V ~ 3.45 V
• Voltage - Supply, Digital: 3.15 V ~ 3.45 V
• Mounting Type: Surface Mount
• Package / Case: 156-LBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935282683518; SAA7105E/V1/G-T; SAA7105E/V1/G-T

Philips Semiconductors
SAA7104E_SAA7105E_2
Product data sheet
Table 58:
[1]
Table 59:
Table 60:
Legend: * = default value after reset.
Subaddress Bit
7Eh
7Fh
Subaddress Bit
81h
82h
83h
Bit
7
6
5
4
3 and 2 PCLE[1:0] R/W
1 and 0 PCLI[1:0]
This bit mask is effective only if the lines are enabled by TTXOVS/TTXOVE and TTXEVS/TTXEVE.
Symbol
DCLK
PCLSY
IFRA
IFBP
Disable TTX line registers, subaddresses 7Eh and 7Fh, bit description
Pixel clock 0, 1 and 2 registers, subaddresses 81h to 83h, bit description
Pixel clock control register, subaddress 84h, bit description
7 to 0 LINE[12:5]
7 to 0 LINE[20:13] R/W
7 to 0 PCL[07:00] R/W
7 to 0 PCL[15:08]
7 to 0 PCL[23:16]
Access Value Description
R/W
R/W
R/W
R/W
R/W
Symbol
Symbol
Rev. 02 — 23 December 2005
0*
1
0*
1
0
1*
0
1*
00
01*
10
11
00
01*
10
11
Access Value
Access Value Description
R/W
set to logic 1
set to logic 1
pixel clock generator
runs free
gets synchronized with the vertical sync
input FIFO gets reset
explicitly at falling edge
every field
input FIFO
active
bypassed
divider ratio for PIXCLK output is 1
divider ratio for PIXCLK output is 2
divider ratio for PIXCLK output is 4
divider ratio for PIXCLK output is 8
controls the divider for the internal pixel clock
divider ratio for internal PIXCLK is 1
divider ratio for internal PIXCLK is 2
divider ratio for internal PIXCLK is 4
not allowed
controls the divider for the external pixel clock
20 F63Bh 640
1B 5A73h 640
-
-
SAA7104E; SAA7105E
individual lines in both fields (PAL counting)
can be disabled for insertion of teletext by the
respective bits, disabled line = LINExx (50 Hz
field rate)
Description
defines the frequency of the synthesized
pixel clock PIXCLKO;
f
pins)
f
XTAL
PIXCLK
= 27 MHz nominal
480 to NTSC M
480 to PAL B/G (as by strapping
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
=
PCL
---------- -
2
24
Digital video encoder
f
XTAL
[1]
8
;
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