AD1893JN Analog Devices Inc, AD1893JN Datasheet
AD1893JN
Specifications of AD1893JN
Related parts for AD1893JN
AD1893JN Summary of contents
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FEATURES Low Cost LQFP and PDIP Packages 3 V Supply Performance Specified—Very Low Power Automatically Senses Sample Frequencies—No Programming Required Rejects Sample Clock Jitter Accommodates Dynamically Changing Asynchronous Sample Clocks 8 kHz to 56 kHz Sample Clock Frequency Range ...
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AD1893–SPECIFICATIONS TEST CONDITIONS UNLESS OTHERWISE NOTED Supply Voltage +3.0 Ambient Temperature 25 Crystal Frequency 16 Load Capacitance 100 All minimums and maximums tested except as noted. 1 PERFORMANCE (Guaranteed for V Dynamic Range ( kHz, –60 dB ...
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... Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Specifications subject to change without notice. Model AD1893JN AD1893JST CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection ...
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AD1893 (continued from Page 1) PRODUCT OVERVIEW (Continued) limited to avoid alias distortion on the output signal. The AD1893 dynamically alters the low-pass filter cutoff frequency smoothly and slowly, so that real-time variations in the sample rate ratio are possible ...
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DIP XTAL_O 1 SERIAL IN 2 XTAL_I DATA_I 3 SERIAL OUT BCLK_I 4 WCLK_I 5 ACCUM 6 LR_I GND MULT NC 9 BKPOL_I 10 FIFO COEF ROM MODE0_I 11 12 MODE1_I RESET 13 CLOCK TRACKING GND ...
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AD1893 Output Control Signals Pin Name DIP LQFP I/O Description BKPOL_O Bit clock polarity. LO: Normal mode. Output data is valid on rising edges of BCLK_O, changed on falling. HI: Inverted mode. Output data is valid on ...
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THEORY OF OPERATION There are at least two logically equivalent methods of explaining the concept of asynchronous sample rate conversion: the high speed interpolation/decimation model and the polyphase filter bank model. Using the AD1893 SamplePort does not require understanding either ...
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AD1893 Polyphase Filter Bank Model Although less intuitively understandable than the interpolation/ decimation model, the polyphase filter bank model is useful to explore because it more accurately portrays the operation of the actual AD1893 SamplePort hardware. In the polyphase filter ...
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AMP Figure 3. Four Polyphase Subfilters Realigned to Coarse Time Grid POLYPHASE FILTER 1 POLYPHASE FILTER 2 POLYPHASE FILTER 3 POLYPHASE FILTER 4 POLYPHASE FILTER 5 POLYPHASE FILTER 6 INPUT POLYPHASE FILTER 7 SIGNAL POLYPHASE FILTER N-1 POLYPHASE FILTER N ...
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AD1893 OFFSET INTO DENSE FIR FILTER COEFFICIENT ARRAY TO ACCESS REQUIRED POLYPHASE FILTER REQUIRED FILTER GROUP DELAY TO COMPUTE REQUESTED OUTPUT SAMPLE A INPUT SEQUENCE PAST OUTPUT SEQUENCE Figure 5. Input and Output Clock Event Relationship A short delay corresponds ...
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Sample Clock Jitter Rejection The loop filter settling time also affects the ability of the AD1893 ASRC to reject sample clock jitter, since the control loop effectively computes a time weighted average or “esti- mated” new output of many past ...
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AD1893 Cutoff Frequency Modification The final important operating concept of the ASRC is the modi- fication of the filter cutoff frequency when the output sample rate (F ) drops below the input sample rate (F SOUT during downsampling operation. The ...
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OPERATING FEATURES Serial Input/Output Ports The AD1893 uses the frequency of the left/right input clock (LR_ I) and the left/right output clock (LR_O) signals to deter- mine the sample rate ratio, and therefore these signals must run continuously and transition ...
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AD1893 Some applications using multiple AD1893s may desire to use the same master clock frequency for all the SamplePorts, sup- plied by a single crystal. The crystal output can be buffered with a 74HCXX gate and distributed to the other ...
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1/2 6kHz SIN SOUT UP- 42kHz SAMPLING 32 DOWN- 24 SAMPLING 16 42kHz – kHz SIN Figure 12. Allowable Input ...
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AD1893 System Mute The mute function applies to both right and left channels on the AD1893. The user can include a system-specific output mute signal, while retaining the automatic mute feature of the AD1893 by using the circuit shown in ...
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AMPLITUDE – dBFS Figure 19. THD+N vs. Input Amplitude, 44.1 kHz Input Sample Frequency, 48 kHz Output Sample Frequency, 1 kHz and ...
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AD1893 BCLK_I, BCLK_O NORMAL MODE INPUT BCLK_I, BCLK_O INVERTED MODE LR_I, LR_O INPUT WCLK_I, WCLK_O INPUT DATA IN/OUT Figure 23. Serial Data Input and Output Timing, Word Clock Triggered Mode BCLK_I, BCLK_O NORMAL MODE INPUT BCLK_I, BCLK_O INVERTED MODE LR_I, ...
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CRYSTAL t CRYSTAL Figure 26. Clock Timing BCLK_I, BCLK_O BCLK_I, BCLK_O INVERTED MODE NO MSB DELAY MODE NO MSB DELAY MODE MSB DELAY MODE MSB DELAY MODE Figure 28. Bit Clock, Word Clock, Left / Right Clock and Data Timing ...
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AD1893 0.250 (6.35) MAX 0.200 (5.05) 0.125 (3.18) OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead Plastic DIP (N-28) 1.565 (39.70) 1.380 (35.10 0.580 (14.73) 0.485 (12.32 0.625 (15.87) PIN 1 0.060 (1.52) 0.600 (15.24) ...