STA013$ STMicroelectronics, STA013$ Datasheet - Page 7

• Manufacturer Part Number: STA013$
• Description: DECODER AUDIO MPEG 2.5 28-SOIC
• Manufacturer: STMicroelectronics
• Type: Audio Decoderr

Specifications of STA013$

• Applications: Sound Cards, Players, Recorders
• Voltage - Supply, Digital: 2.4 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• Audio Codec Type: MP3 Decoder
• No. Of Dacs: 1
• No. Of Input Channels: 2
• No. Of Output Channels: 2
• Sampling Rate: 48kSPS
• Interface Type: I2C, Serial
• Supply Voltage Range: 2.4V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply, Analog: -
• Lead Free Status / Rohs Status: Compliant

Figure 5. MPEG Decoder Interfaces.
Figure 6. Serial Input Interface Clocks
2.2 - Serial Input Interface
STA013 receives the input data (MSB first)
thought the Serial Input Interface (Fig.5). It is a
serial communication interface connected to the
SDI (Serial Data Input) and SCKR (Receiver Se-
rial Clock).
The interface can be configured to receive data
sampled on both rising and falling edge of the
SCKR clock.
The BIT_EN pin, when set to low, forces the bit-
stream input interface to ignore the incoming
data. For proper operation Bit-E
toggled only when SCR is stable low (for both
SCLK_POL configuration) The possible configu-
rations are described in Fig. 6.
SOURCE
DATA
BIT_EN
D98AU912
SCKR
SCKR
SDI
DATA_REQ
BIT_EN
SCKR
SDI
DATA VALID
N
line shold be
XTI
SERIAL AUDIO INTERFACE
XTO
PLL
RX
D98AU968A
DECODER
FILT
MPEG
SCL
2.3 - PLL & Clock Generator System
When STA013 receives the input clock, as de-
scribed in Section 2.1, and a valid layer III input
bit stream, the internal PLL locks, providing to the
DSP Core the master clock (DCLK), and to the
Audio Output Interface the nominal frequencies of
the incoming compressed bit stream. The STA013
PLL block diagram is described in Figure 7.
The audio sample rates are obtained dividing the
oversampling clock (OCLK) by software program-
mable factors. The operation is done by STA013
embedded software and it is transparent to the
user.
The STA013 PLL can drive directly most of the
commercial DACs families, providing an over
sampling clock, OCLK, obtained dividing the VCO
frequency with a software programmable dividers.
IIC
IIC
TX
P
SDA
DATA IGNORED
DATA
IGNORED
STA013 - STA013B - STA013T
SDO
SCKT
LRCKT
SCLK_POL=0
SCLK_POL=4
OCLK
DAC
7/38