ADV7194KSTZ Analog Devices Inc, ADV7194KSTZ Datasheet - Page 36

• Manufacturer Part Number: ADV7194KSTZ
• Description: IC ENCODER VIDEO EXT-10 80-LQFP
• Manufacturer: Analog Devices Inc
• Type: Video Encoderr

Specifications of ADV7194KSTZ

• Applications: DVD, PC Video, Multimedia
• Voltage - Supply, Analog: 3.3 V ~ 5 V
• Voltage - Supply, Digital: 3.3 V ~ 5 V
• Mounting Type: Surface Mount
• Package / Case: 80-LQFP
• Input Format: Digital
• Output Format: Analog
• Supply Voltage Range: 3.15V To 3.6V
• Operating Temperature Range: 0°C To +70°C
• Tv / Video Case Style: LQFP
• No. Of Pins: 80
• Msl: MSL 1 - Unlimited
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADV7194EB - BOARD EVAL FOR ADV7194
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADV7194
Chroma Delay Control (MR95–MR97)
The Chroma signal can be delayed by up to eight clock cycles
at 27 MHz using MR94–95. For further information see also
the Chroma/Luma Delay section.
TIMING REGISTER 0 (TR07–TR00)
(Address (SR4–SR0) = 0AH)
Figure 66 shows the various operations under the control of
Timing Register 0. This register can be read from as well as
written to.
TR0 BIT DESCRIPTION
Master/Slave Control (TR00)
This bit controls whether the ADV7194 is in master or slave mode.
Timing Mode Selection (TR01–TR02)
These bits control the timing mode of the ADV7194. These
modes are described in more detail in the Timing and Con-
trol section of the data sheet.
BLANK Input Control (TR03)
This bit controls whether the BLANK input is used to accept
blank signals or whether blank signals are internally generated.
Note: When this input pin is tied high (to 5 V), the input is dis-
abled regardless of the register setting. It, therefore, should be
tied low (to Ground) to allow control over the I
Luma Delay (TR04–TR05)
The luma signal can be delayed by up to 222 ns (or six clock
cycles at 27 MHz) using TR04–05. For further information see
Chroma/Luma Delay section.
Min Luminance Value (TR06)
This bit is used to control the minimum luma output value
by the ADV7194. When this bit is set to a Logic 1, the luma is
limited to 7IRE below the blank level. When this bit is set to (0),
the luma value can be as low as the sync bottom level.
Timing Register Reset (TR07)
Toggling TR07 from low to high and low again resets the inter-
nal timing counters. This bit should be toggled after power-up,
reset or changing to a new timing mode.
TO THESE BITS
MR97 MR96
BE WRITTEN
TR07
ZERO MUST
REGISTER RESET
MIN LUMINANCE VALUE
TR06
MR97
TIMING
0
1
TR07
LUMA MIN =
SYNC BOTTOM
LUMA MIN =
BLANK –7.5 IRE
MR96
MR95 MR94
TR06
0
0
1
1
DELAY CONTROL
0
1
0
1
CHROMA
2
MR95
C register.
0ns DELAY
148ns DELAY
296ns DELAY
RESERVED
TR05
TR05 TR04
0
0
1
1
LUMA DELAY
0
1
0
1
MR94
TR04
0ns DELAY
74ns DELAY
148ns DELAY
222ns DELAY
MR93
BLACK BURST
LUMA DAC
0
1
TR03
0
1
BLANK INPUT
DISABLE
ENABLE
CONTROL
MR93
TR03
TIMING REGISTER 1
(TR17–TR10)
(Address (SR4–SR0) = 0BH)
Timing Register 1 is an 8-bit-wide register.
Figure 67 shows the various operations under the control of
Timing Register 1. This register can be read from as well written
to. This register can be used to adjust the width and position of
the master mode timing signals.
TR1 BIT DESCRIPTION
HSYNC Width (TR10–TR11)
These bits adjust the HSYNC pulsewidth.
T
HSYNC to VSYNC Delay Control (TR13–TR12)
These bits adjust the position of the HSYNC output relative to
the VSYNC output.
T
HSYNC to VSYNC Rising Edge Control (TR14–TR15)
When the ADV7194 is in Timing Mode 1, these bits adjust the
position of the HSYNC output relative to the VSYNC output ris-
ing edge.
T
VSYNC Width (TR14–TR15)
When the ADV7194 is configured in Timing Mode 2, these bits
adjust the VSYNC pulsewidth.
T
HSYNC to Pixel Data Adjust (TR16–TR17)
This enables the HSYNC to be adjusted with respect to the
pixel data. This allows the Cr and Cb components to be swapped.
This adjustment is available in both master and slave timing
modes.
T
ENABLE
DISABLE
PCLK
PCLK
PCLK
PCLK
PCLK
= one clock cycle at 27 MHz.
= one clock cycle at 27 MHz.
= one clock cycle at 27 MHz.
= one clock cycle at 27 MHz.
= one clock cycle at 27 MHz.
MR92
BLACK BURST
TR02 TR01
MR92
0
1
TR02
0
0
1
1
Y-DAC
TIMING MODE
DISABLE
SELECTION
ENABLE
0
1
0
1
MODE 0
MODE 1
MODE 2
MODE 3
MR91
TR01
MR91 MR90
TR00
0
0
1
1
0
1
MASTER / SLAVE
UNDERSHOOT
CONTROL
SLAVE TIMING
MASTER TIMING
MR90
0
LIMITER
1
0
1
TR00
DISABLED
–11 IRE
–6 IRE
–1.5 IRE