SFPA8192Q1BO2TO-I-QT-223-STD Swissbit NA Inc, SFPA8192Q1BO2TO-I-QT-223-STD Datasheet - Page 24

• Manufacturer Part Number: SFPA8192Q1BO2TO-I-QT-223-STD
• Description: FLASH SSD SMART UDMA 2.5" 8GB
• Manufacturer: Swissbit NA Inc
• Series: P-120r

Specifications of SFPA8192Q1BO2TO-I-QT-223-STD

• Memory Size: 8GB
• Memory Type: FLASH
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 1052-1025

Figure 7: Ultra DMA Data-In Burst Host Termination Timing
Notes: The definitions for the STOP, HDMARDY, and DSTROBE signal lines are no longer in effect after
DMARQ and DMACK are negated.
6.3.2.4.6 Initiating an Ultra DMA Data-Out Burst
An Ultra DMA Data-out burst is initiated by following the steps lettered below. The timing diagram
is shown in Figure 8: Ultra DMA Data-Out Burst Initiation Timing. The timing parameters are
specified in Table 22: Ultra DMA Data Burst Timing Requirements and are described in Table 23: Ultra DMA
Data Burst Timing Descriptions.
The following steps shall occur in the order they are listed unless otherwise specifically allowed:
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j)
k) The host shall negate -DMACK no sooner than t
l)
m) The device shall compare the CRC data received from the host with the results of its own CRC
n) The device shall release DSTROBE within t
o) The host shall neither negate STOP nor assert -HDMARDY until at least t
p) The host shall not assert -IORD, -CS0, -CS1, DA2, DA1, or DA0 until at least t
a) The host shall keep -DMACK in the negated state before an Ultra DMA burst is initiated.
b) The device shall assert DMARQ to initiate an Ultra DMA burst.
c)
d) The host shall assert HSTROBE.
If the host has not placed the result of its CRC calculation on D[15:00] since first driving D[15:00]
during (9), the host shall place the result of its CRC calculation on D[15:00] (see 6.3.2.5 ).
DMARQ and the host has asserted STOP and negated -HDMARDY, and no sooner than t
host places the result of its CRC calculation on D[15:00].
The device shall latch the host’s CRC data from D[15:00] on the negating edge of -DMACK.
calculation. If a miscompare error occurs during one or more Ultra DMA burst for any one command,
at the end of the command, the device shall report the first error that occurred (see 6.3.2.5 ).
-DMACK.
Steps (c), (d), and (e) may occur in any order or at the same time. The host shall assert STOP.
Swissbit reserves the right to change products or specifications without notice.
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IORDYZ
after the host negates -DMACK.
MLI
after the device has asserted DSTROBE and negated
P-120_data_sheet_PA-QxBO_Rev100.doc
ACK
after the host has negated
ACK
after negating DMACK.
DVS
after the
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