LFEC6E-5FN484C Lattice, LFEC6E-5FN484C Datasheet - Page 11

• Manufacturer Part Number: LFEC6E-5FN484C
• Description: FPGA - Field Programmable Gate Array 6.1 LUT 224 I/O
• Manufacturer: Lattice

Specifications of LFEC6E-5FN484C

• Number Of Gates: 6100
• Number Of Logic Blocks: 768
• Number Of Macrocells: 6100
• Maximum Operating Frequency: 420 MHz
• Number Of Programmable I/os: 224
• Data Ram Size: 94208
• Delay Time: 5 ns
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Package / Case: FPBGA-484
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: *
• Number Of I /o: *
• Voltage - Supply: *
• Mounting Type: *
• Operating Temperature: *
• Lead Free Status / Rohs Status: Details

Lattice Semiconductor
Secondary Clock Sources
LatticeECP/EC devices have four secondary clock resources per quadrant. The secondary clock branches are
tapped at every PFU. These secondary clock networks can also be used for controls and high fanout data. These
secondary clocks are derived from four clock input pads and 16 routing signals as shown in Figure 2-7.
Figure 2-7. Secondary Clock Sources
Clock Routing
The clock routing structure in LatticeECP/EC devices consists of four Primary Clock lines and a Secondary Clock
network per quadrant. The primary clocks are generated from MUXs located in each quadrant. Figure 2-8 shows
this clock routing. The four secondary clocks are generated from MUXs located in each quadrant as shown in
Figure 2-9. Each slice derives its clock from the primary clock lines, secondary clock lines and routing as shown in
Figure 2-10.
From Routing
From Routing
From Routing
From Routing
Routing
Routing
From
From
Routing
Routing
20 Secondary Clock Sources
To Quadrant Clock Selection
From
From
2-8
Routing
Routing
From
From
LatticeECP/EC Family Data Sheet
Routing
Routing
From
From
From Routing
From Routing
From Routing
From Routing
Architecture