LFE2-12SE-5TN144C Lattice, LFE2-12SE-5TN144C Datasheet - Page 96

• Manufacturer Part Number: LFE2-12SE-5TN144C
• Description: FPGA - Field Programmable Gate Array 12K LUTs S-Series 1.1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFE2-12SE-5TN144C

• Number Of Macrocells: 12000
• Maximum Operating Frequency: 320 MHz
• Number Of Programmable I/os: 93
• Data Ram Size: 226304
• Delay Time: 12 ns
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Package / Case: TQFP-144
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Lead Free Status / Rohs Status: Details

LatticeECP2/M sysCONFIG Port Timing Specifications (Continued)
Lattice Semiconductor
Figure 3-14. sysCONFIG Parallel Port Read Cycle
Figure 3-15. sysCONFIG Parallel Port Write Cycle
t
t
Timing v.A 0.11
Master Clock Frequency
Duty Cycle
Timing v.A 0.11
SUSPI
HSPI
Parameter
Parameter
WRITEN
WRITEN
SOSPI Data Setup Time Before CCLK
SOSPI Data Hold Time After CCLK
CCLK
CS1N
BUSY
D[0:7]
*n = last byte of read cycle.
CCLK
CS1N
BUSY
D[0:7]
*n = last byte of write cycle.
CSN
CSN
Selected value - 30%
Over Recommended Operating Conditions
t
SUCBDI
Min.
40
t
t
t
t
Description
SUWD
SUCS
SUWD
SUCS
Byte 0
Byte 0
t
t
BSCL
BSCL
3-45
Byte 1
Byte 1
t
t
CORD
HCBDI
Selected value + 30%
Byte 2
Max.
t
t
60
DCB
DCB
DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
t
Byte 2
BSCYC
t
t
BSCH
BSCH
Byte n*
Byte n*
t
Min.
HCS
t
t
t
7
2
HCS
HWD
HWD
Units
MHz
Max.
%
—
—
Units
ns
ns