LFE2-12SE-5TN144C Lattice, LFE2-12SE-5TN144C Datasheet - Page 36

• Manufacturer Part Number: LFE2-12SE-5TN144C
• Description: FPGA - Field Programmable Gate Array 12K LUTs S-Series 1.1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFE2-12SE-5TN144C

• Number Of Macrocells: 12000
• Maximum Operating Frequency: 320 MHz
• Number Of Programmable I/os: 93
• Data Ram Size: 226304
• Delay Time: 12 ns
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Package / Case: TQFP-144
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Lead Free Status / Rohs Status: Details

Lattice Semiconductor
Figure 2-31. Output and Tristate Block for Left, Right and Bottom Edges
DQSXFER
DQSXFER
ONEG1
ONEG0
ONEG1
ONEG0
OPOS1
OPOS0
OPOS1
OPOS0
(CLKA)
(CLKB)
ECLK1
ECLK2
ECLK1
ECLK2
CLKA
CLKB
CLK1
CLK1
TD
TD
* Shared with input register
Clock Transfer
Clock Transfer
Registers
Registers
D
D
D-Type*
D-Type*
D-Type
D-Type
D
D
Tristate Logic
Tristate Logic
Q
Q
Q
Q
*
*
D
D
Latch
Latch
Q
Q
0
1
0
1
0
1
0
1
2-33
Note: Simplified version does not show CE and SET/RESET details
0
1
0
1
0
1
0
1
D
D
D
D
D
D
D
D
/LATCH
/LATCH
/LATCH
/LATCH
D-Type
D-Type
D-Type
D-Type
D-Type
D-Type
D-Type
D-Type
LatticeECP2/M Family Data Sheet
Q
Q
Q
Q
Q
Q
Q
Q
Comp PIO (B) in LVDS I/O Pair
True PIO (A) in LVDS I/O Pair
D
D
D
D
DDR Output
DDR Output
Latch
Latch
Latch
Latch
Registers
Registers
Q
Q
Q
Q
Output Logic
Output Logic
0
1
0
1
0
1
0
1
0
1
0
1
Programmable
Programmable
Control
Control
0
1
0
1
Architecture
0
1
0
1
DO
DO
TO
TO