CP2110-F02-GM1 Silicon Laboratories Inc, CP2110-F02-GM1 Datasheet - Page 13

• Manufacturer Part Number: CP2110-F02-GM1
• Description: Peripheral Drivers & Components (PCIs) HID USB-UART bridge
• Manufacturer: Silicon Laboratories Inc

Specifications of CP2110-F02-GM1

• Package / Case: QFN-28
• Input Voltage Range (max): 5.25 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 12.5 mA
• Lead Free Status / Rohs Status: Details

Notes:
General
Solder Mask Design
Stencil Design
Card Assembly
Dimension
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
7. A 2 x 2 array of 1.10 x 1.10 mm openings on a 1.30 mm pitch should be used for the center
8. A No-Clean, Type-3 solder paste is recommended.
9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small
C1
C2
X1
E
mask and the metal pad is to be 60 m minimum, all the way around the pad.
to assure good solder paste release.
pad.
Body Components.
Figure 5. QFN-24 Recommended PCB Land Pattern
Table 9. QFN-24 PCB Land Pattern Dimensions
3.90
3.90
0.20
Min
0.50 BSC
Max
4.00
4.00
0.30
Rev. 1.1
Dimension
X2
Y1
Y2
2.70
0.65
2.70
Min
Max
2.80
0.75
2.80
CP2110
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