SAK-C505CA-4RM CA Infineon Technologies, SAK-C505CA-4RM CA Datasheet - Page 42

• Manufacturer Part Number: SAK-C505CA-4RM CA
• Description: Microcontrollers (MCU) 8-Bit Single Chip Microcontroller
• Manufacturer: Infineon Technologies

Specifications of SAK-C505CA-4RM CA

• Data Bus Width: 8 bit
• Program Memory Type: ROM
• Program Memory Size: 32 KB
• Data Ram Size: 1.25 KB
• Interface Type: USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 3
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: PG-MQFP-44
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Packages: PG-MQFP-44
• Max Clock Frequency: 20.0 MHz
• Sram (incl. Cache): 1.25 KByte
• Can Nodes: 1
• A / D Input Lines (incl. Fadc): 8
• Program Memory: 32.0 KByte
• Lead Free Status / Rohs Status: No
• Other names: K505CA4RMCANT

8-Bit A/D Converter (C505 and C505C only)
The C505/C505C includes a high performance / high speed 8-bit A/D converter (ADC) with 8 analog
input channels. It operates with a successive approximation technique and provides the following
features:
The 8-bit ADC uses two clock signals for operation : the conversion clock f
input clock f
pins via the ADC clock prescaler as shown in
conversion clock f
prescaler must be programmed to a value which assures that the conversion clock does not exceed
1.25 MHz. The prescaler ratio is selected by the bits ADCL1 and ADCL0 of SFR ADCON1.
Figure 17
8-Bit A/D Converter Clock Selection
Data Sheet
– 8 multiplexed input channels (port 1), which can also be used as digital outputs/inputs
– 8-bit resolution
– Internal start-of-conversion trigger
– Interrupt request generation after each conversion
– Single or continuous conversion mode
MCU System Clock
Rate (f
10 MHz
12 MHz
16 MHz
20 MHz
2 MHz
5 MHz
6 MHz
IN
OSC
(1/t
Condition:
f
OSC
IN
ADC
)
). f
ADC
is limited to a maximum frequency of 1.25 MHz. Therefore, the ADC clock
f
ADC max
is derived from the C505 system clock f
ADCL1
Clock Prescaler
32
16
f
[MHz]
10
12
16
20
8
4
IN
2
5
6
< 1.25 MHz
MUX
ADCL0
Prescaler
Ratio
f
4
4
8
8
16
16
16
Conversion Clock
IN
= f
Figure
38
OSC
Input Clock
=
f
[MHz]
0.5
1.25
0.75
1.25
0.75
1
1.25
CLP
ADC
17. The input clock is equal to f
1
f
C505/C505C/C505A/C505CA
ADC
f
IN
OSC
ADCL1
0
0
0
0
1
1
1
Converter
which is applied at the XTAL
A / D
MCS03299
ADC
ADCL0
0
0
1
1
0
0
0
(=1/t
ADC
OSC
) and the
12.00
. The