SAK-C505CA-4RM CA Infineon Technologies, SAK-C505CA-4RM CA Datasheet - Page 25

• Manufacturer Part Number: SAK-C505CA-4RM CA
• Description: Microcontrollers (MCU) 8-Bit Single Chip Microcontroller
• Manufacturer: Infineon Technologies

Specifications of SAK-C505CA-4RM CA

• Data Bus Width: 8 bit
• Program Memory Type: ROM
• Program Memory Size: 32 KB
• Data Ram Size: 1.25 KB
• Interface Type: USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 3
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: PG-MQFP-44
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Packages: PG-MQFP-44
• Max Clock Frequency: 20.0 MHz
• Sram (incl. Cache): 1.25 KByte
• Can Nodes: 1
• A / D Input Lines (incl. Fadc): 8
• Program Memory: 32.0 KByte
• Lead Free Status / Rohs Status: No
• Other names: K505CA4RMCANT

Table 3
Special Function Registers - Functional Blocks (cont’d)
Block
CAN
Controller
(C505C/
C505CA
Data Sheet
1) Bit-addressable special function registers
2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks.
3) “X“ means that the value is undefined and the location is reserved. “U“ means that the value is unchanged by
4) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.
5) The notation “n“ (n= 1 to F) in the message object address definition defines the number of the related
only)
message object.
a reset operation. “U“ values are undefined (as “X“) after a power-on reset operation
Symbol
CR
SR
IR
BTR0
BTR1
GMS0
GMS1
UGML0
UGML1
LGML0
LGML1
UMLM0
UMLM1
LMLM0
LMLM1
MCR0
MCR1
UAR0
UAR1
LAR0
LAR1
MCFG
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
Name
Control Register
Status Register
Interrupt Register
Bit Timing Register Low
Bit Timing Register High
Global Mask Short Register Low
Global Mask Short Register High
Upper Global Mask Long Register Low
Upper Global Mask Long Register High
Lower Global Mask Long Register Low
Lower Global Mask Long Register High
Upper Mask of Last Message Register Low
Upper Mask of Last Message Register High
Lower Mask of Last Message Register Low
Lower Mask of Last Message Register High
Message Object Registers :
Message Control Register Low
Message Control Register High
Upper Arbitration Register Low
Upper Arbitration Register High
Lower Arbitration Register Low
Lower Arbitration Register High
Message Configuration Register
Message Data Byte 0
Message Data Byte 1
Message Data Byte 2
Message Data Byte 3
Message Data Byte 4
Message Data Byte 5
Message Data Byte 6
Message Data Byte 7
21
C505/C505C/C505A/C505CA
Address Contents after
F700 H
F701 H
F702 H
F704 H
F705 H
F706 H
F707 H
F708 H
F709 H
F70A H
F70B H
F70C H
F70D H
F70E H
F70F H
F7n0 H
F7n1 H
F7n2 H
F7n3 H
F7n4 H
F7n5 H
F7n6 H
F7n7 H
F7n8 H
F7n9 H
F7nA H
F7nB H
F7nC H
F7nD H
F7nE H
5)
5)
5)
5)
5)
5)
5)
5)
5)
5)
5)
5)
5)
5)
5)
Reset
01 H
XX H
XX H
UU H
0UUUUUUU
UU H
UUU11111
UU H
UU H
UU H
UUUUU000
UU H
UU H
UU H
UUUUU000
UU H
UU H
UU H
UU H
UU H
UUUUU000
UUUUUU00
XX H
XX H
XX H
XX H
XX H
XX H
XX H
XX H
3)
3)
3)
3)
3)
3)
3)
3)
3)
3)
3)
3)
3)
3)
3)
3)
3)
3)
3)
3)
3)
3)
3)
12.00
B
B
B
B
B
B
3)
3)
3)
3)
3)
3)