LPC11C22FBD48/301,151 NXP Semiconductors, LPC11C22FBD48/301,151 Datasheet - Page 18
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LPC11C22FBD48/301,151
Manufacturer Part Number
LPC11C22FBD48/301,151
Description
Microcontrollers (MCU) CAN Transceiver MCU 16K Flash
Manufacturer
NXP Semiconductors
Datasheet
1.LPC11C22FBD48301151.pdf
(62 pages)
Specifications of LPC11C22FBD48/301,151
Processor Series
LPC11Cx2
Core
ARM Cortex-M0
Data Bus Width
32 bit
Program Memory Type
Flash
Program Memory Size
16 KB
Data Ram Size
8 KB
Interface Type
CAN, I2C, SPI, UART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
36
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
OM13012,598
Minimum Operating Temperature
- 40 C
Lead Free Status / Rohs Status
Details
Other names
935294284151
NXP Semiconductors
LPC11CX2_CX4
Product data sheet
7.8.1 Features
7.9.1 Features
7.10 I
7.8 UART
7.9 SPI serial I/O controller
The LPC11Cx2/Cx4 contain one UART.
Support for RS-485/9-bit mode allows both software address detection and automatic
address detection using 9-bit mode.
The UART includes a fractional baud rate generator. Standard baud rates such as
115200 Bd can be achieved with any crystal frequency above 2 MHz.
The LPC11Cx2/Cx4 contain two SPI controllers. Both SPI controllers support SSP
features.
The SPI controller is capable of operation on a SSP, 4-wire SSI, or Microwire bus. It can
interact with multiple masters and slaves on the bus. Only a single master and a single
slave can communicate on the bus during a given data transfer. The SPI supports full
duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the
slave and from the slave to the master. In practice, often only one of these data flows
carries meaningful data.
The LPC11Cx2/Cx4 contain one I
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C-bus serial I/O controller
Maximum UART data bit rate of 3.125 Mbit/s.
16 Byte Receive and Transmit FIFOs.
Register locations conform to 16C550 industry standard.
Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.
Built-in fractional baud rate generator covering wide range of baud rates without a
need for external crystals of particular values.
FIFO control mechanism that enables software flow control implementation.
Support for RS-485/9-bit mode.
Support for modem control.
Maximum SPI speed of 25 Mbit/s (master) or 4.17 Mbit/s (slave) (in SSP mode)
Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National
Semiconductor Microwire buses
Synchronous serial communication
Master or slave operation
8-frame FIFOs for both transmit and receive
4-bit to 16-bit frame
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 27 June 2011
2
C-bus controller.
32-bit ARM Cortex-M0 microcontroller
LPC11Cx2/Cx4
© NXP B.V. 2011. All rights reserved.
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