LPC11C22FBD48/301,151 NXP Semiconductors, LPC11C22FBD48/301,151 Datasheet - Page 15
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LPC11C22FBD48/301,151
Manufacturer Part Number
LPC11C22FBD48/301,151
Description
Microcontrollers (MCU) CAN Transceiver MCU 16K Flash
Manufacturer
NXP Semiconductors
Datasheet
1.LPC11C22FBD48301151.pdf
(62 pages)
Specifications of LPC11C22FBD48/301,151
Processor Series
LPC11Cx2
Core
ARM Cortex-M0
Data Bus Width
32 bit
Program Memory Type
Flash
Program Memory Size
16 KB
Data Ram Size
8 KB
Interface Type
CAN, I2C, SPI, UART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
36
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
OM13012,598
Minimum Operating Temperature
- 40 C
Lead Free Status / Rohs Status
Details
Other names
935294284151
NXP Semiconductors
7. Functional description
LPC11CX2_CX4
Product data sheet
7.1 ARM Cortex-M0 processor
7.2 On-chip flash program memory
7.3 On-chip SRAM
7.4 Memory map
The ARM Cortex-M0 is a general purpose, 32-bit microprocessor, which offers high
performance and very low power consumption.
The LPC11Cx2/Cx4 contain 32 kB (LPC11C14/C24) or 16 kB (LPC11C12/C22) of on-chip
flash program memory.
The LPC11Cx2/Cx4 contain a total of 8 kB on-chip static RAM data memory.
The LPC11Cx2/Cx4 incorporates several distinct memory regions, shown in the following
figures.
program viewpoint following reset. The interrupt vector area supports address remapping.
The AHB peripheral area is 2 megabyte in size, and is divided to allow for up to 128
peripherals. The APB peripheral area is 512 kB in size and is divided to allow for up to 32
peripherals. Each peripheral of either type is allocated 16 kilobytes of space. This allows
simplifying the address decoding for each peripheral.
Figure 4
All information provided in this document is subject to legal disclaimers.
shows the overall map of the entire address space from the user
Rev. 3 — 27 June 2011
32-bit ARM Cortex-M0 microcontroller
LPC11Cx2/Cx4
© NXP B.V. 2011. All rights reserved.
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