ST72T631K4M1 STMicroelectronics, ST72T631K4M1 Datasheet - Page 18

• Manufacturer Part Number: ST72T631K4M1
• Description: Microcontrollers (MCU) OTP EPROM 16K USB/SC
• Manufacturer: STMicroelectronics

Specifications of ST72T631K4M1

• Data Bus Width: 8 bit
• Program Memory Type: EPROM
• Program Memory Size: 16 KB
• Data Ram Size: 512 B
• Interface Type: I2C, SCI, USB
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 19
• Number Of Timers: 2
• Operating Supply Voltage: 4 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: SO-34
• Minimum Operating Temperature: 0 C
• On-chip Adc: 8 bit
• Lead Free Status / Rohs Status: No

ST7263
3.2 RESET
The Reset procedure is used to provide an orderly
software start-up or to exit low power modes.
Three reset modes are provided: a low voltage
(LVD) reset, a watchdog reset and an external re-
set at the RESET pin.
A reset causes the reset vector to be fetched from
addresses FFFEh and FFFFh in order to be loaded
into the PC and with program execution starting
from this point.
An internal circuitry provides a 4096 CPU clock cy-
cle delay from the time that the oscillator becomes
active.
3.2.1 Low Voltage Detector (LVD)
Low voltage reset circuitry generates a reset when
V
Table 6. List of sections affected by RESET, WAIT and HALT (Refer to 3.5 for Wait and Halt Modes)
18/109
DD
CPU clock running at 8 MHz
Timer Prescaler reset to zero
Timer Counter set to FFFCh
All Timer enable bit set to 0 (disable)
Data Direction Registers set to 0 (as Inputs)
Set Stack Pointer to 013Fh
Force Internal Address Bus to restart vector FFFEh,FFFFh
Set Interrupt Mask Bit (I-Bit, CCR) to 1 (Interrupt Disable)
Set Interrupt Mask Bit (I-Bit, CCR) to 0 (Interrupt Enable)
Reset HALT latch
Reset WAIT latch
Disable Oscillator (for 4096 cycles)
Set Timer Clock to 0
Watchdog counter reset
Watchdog register reset
Port data registers reset
Other on-chip peripherals: registers reset
below V
below V
is:
IT+
IT-
when V
when V
DD
DD
is falling.
is rising,
Section
During low voltage reset, the RESET pin is held low,
thus permitting the MCU to reset other devices.
The Low Voltage Detector can be disabled by set-
ting the LVD bit of the Miscellaneous Register.
3.2.2 Watchdog Reset
When a watchdog reset occurs, the RESET pin is
pulled low permitting the MCU to reset other devic-
es in the same way as the low voltage reset
ure
3.2.3 External Reset
The external reset is an active low input signal ap-
plied to the RESET pin of the MCU.
As shown in
stay low for a minimum of one and a half CPU
clock cycles.
An internal Schmitt trigger at the RESET pin is pro-
vided to improve noise immunity.
11).
Figure
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
RESET
14, the RESET signal must
X
WAIT
X
X
X
HALT
(Fig-