ST72T631K4M1 STMicroelectronics, ST72T631K4M1 Datasheet - Page 77
ST72T631K4M1
Manufacturer Part Number
ST72T631K4M1
Description
Microcontrollers (MCU) OTP EPROM 16K USB/SC
Manufacturer
STMicroelectronics
Datasheet
1.ST72T631K4M1.pdf
(109 pages)
Specifications of ST72T631K4M1
Data Bus Width
8 bit
Program Memory Type
EPROM
Program Memory Size
16 KB
Data Ram Size
512 B
Interface Type
I2C, SCI, USB
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
19
Number Of Timers
2
Operating Supply Voltage
4 V to 5.5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Package / Case
SO-34
Minimum Operating Temperature
0 C
On-chip Adc
8 bit
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ST72T631K4M1
Manufacturer:
SIEMENS
Quantity:
5 510
Part Number:
ST72T631K4M1
Manufacturer:
ST
Quantity:
20 000
I²C BUS INTERFACE (Cont’d)
Figure 40. Transfer Sequencing
Legend:
S=Start, P=Stop, A=Acknowledge, NA=Non-acknowledge
EVx=Event (with interrupt if ITE=1)
Master Transmitter
Slave Receiver
S Address
Slave Transmitter
S Address
Master Receiver
S
S
EV1: EVF=1, ADSL=1, cleared by reading the SR1 register.
EV2: EVF=1, BTF=1, cleared by reading the SR1 register followed by reading the DR register.
EV3: EVF=1, BTF=1, cleared by reading the SR1 register followed by writing the DR register.
EV3-1: EVF=1, AF=1, BTF=1; AF is cleared by reading the SR1 register. The BTF is cleared
by releasing the lines (STOP=1, STOP=0) or by writing the DR register (DR=FFh).
Note: If lines are released by STOP=1, STOP=0, the subsequent EV4 is not seen.
EV4: EVF=1, STOPF=1, cleared by reading the SR2 register.
EV5: EVF=1, SB=1, cleared by reading the SR1 register followed by writing the DR register.
EV6: EVF=1, cleared by reading the SR1 register followed by writing the CR register
(for example PE=1).
EV7: EVF=1, BTF=1, cleared by reading the SR1 register followed by reading the DR register.
EV8: EVF=1, BTF=1, cleared by reading the SR1 register followed by writing the DR register.
EV5
EV5
Address
Address
A
A
EV1 EV3
EV1
A
A
Data1
EV6
EV6 EV8
Data1
Data1
A
Data1
EV2
A
A
EV3
Data2
EV7
A
Data2
EV8
Data2
A
Data2
EV2
A
A
EV3
EV7
.....
A
EV8
.....
DataN
.....
DataN
.....
DataN
A
DataN
EV2
NA
NA
EV3-1
P
EV7
A
EV4
ST7263
EV8
P
P
77/109
EV4
P