SAB-C161PI-L25F CA Infineon Technologies, SAB-C161PI-L25F CA Datasheet - Page 49

• Manufacturer Part Number: SAB-C161PI-L25F CA
• Description: Microcontrollers (MCU) 16BIT SNGL CHIP 5V 25MHz ROM less
• Manufacturer: Infineon Technologies

Specifications of SAB-C161PI-L25F CA

• Data Bus Width: 16 bit
• Program Memory Type: ROMLess
• Data Ram Size: 3 KB
• Interface Type: ASC, I2C, SSC
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 76
• Number Of Timers: 5
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-100
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 4 Channel
• Packages: PG-TQFP-100
• Max Clock Frequency: 25.0 MHz
• Sram (incl. Cache): 3.0 KByte
• A / D Input Lines (incl. Fadc): 4
• Program Memory: 0.0 KByte
• Lead Free Status / Rohs Status: Details
• Other names: B161PIL25FCAXT

The timings listed in the AC Characteristics that refer to TCLs therefore must be
calculated using the minimum TCL that is possible under the respective circumstances.
The actual minimum value for TCL depends on the jitter of the PLL. As the PLL is
constantly adjusting its output frequency so it corresponds to the applied input frequency
(crystal or oscillator) the relative deviation for periods of more than one TCL is lower than
for one single TCL (see formula and figure below).
For a period of N * TCL the minimum value is computed using the corresponding
deviation D
where N = number of consecutive TCLs
So for a period of 3 TCLs @ 25 MHz (i.e. N = 3): D
and (3TCL)
This is especially important for bus cycles using waitstates and e.g. for the operation of
timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train
generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter
is neglectible.
Note: For all periods longer than 40 TCL the N=40 value can be used (see figure below).
Figure 12
Data Sheet
26.5
20
10
1
( N * TCL)
1
Max.jitter D [ns]
This approximated formula is valid for
1
N
min
:
5
Approximated Maximum Accumulated PLL Jitter
= 3TCL
min
40 and 10MHz
= N * TCL
10
NOM
- 1.288 ns = 58.7 ns (@
NOM
f
CPU
- D
20
N
25MHz.
47
and 1
D
N
[ns] = (13.3 + N *6.3) /
3
N
CPU
= (13.3 + 3 * 6.3) / 25 = 1.288 ns,
40.
= 25 MHz).
40
CPU
[MHz],
10 MHz
16 MHz
20 MHz
25 MHz
&3,
1999-07
N