SAB-C161PI-L25F CA Infineon Technologies, SAB-C161PI-L25F CA Datasheet - Page 12

• Manufacturer Part Number: SAB-C161PI-L25F CA
• Description: Microcontrollers (MCU) 16BIT SNGL CHIP 5V 25MHz ROM less
• Manufacturer: Infineon Technologies

Specifications of SAB-C161PI-L25F CA

• Data Bus Width: 16 bit
• Program Memory Type: ROMLess
• Data Ram Size: 3 KB
• Interface Type: ASC, I2C, SSC
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 76
• Number Of Timers: 5
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-100
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 4 Channel
• Packages: PG-TQFP-100
• Max Clock Frequency: 25.0 MHz
• Sram (incl. Cache): 3.0 KByte
• A / D Input Lines (incl. Fadc): 4
• Program Memory: 0.0 KByte
• Lead Free Status / Rohs Status: Details
• Other names: B161PIL25FCAXT

Data Sheet
Table 1
Symbol Pin
RSTIN
RST
OUT
NMI
Num.
TQFP
76
77
78
Pin Definitions and Functions (continued)
Pin
Num.
MQFP
78
79
80
Input
Outp.
I/O
O
I
Function
Reset Input with Schmitt-Trigger characteristics. A low
level at this pin while the oscillator is running resets the
C161PI. An internal pullup resistor permits power-on
reset using only a capacitor connected to
A spike filter suppresses input pulses <10 ns. Input
pulses >100 ns safely pass the filter.
The minimum duration for a safe recognition should be
100 ns + 2 CPU clock cycles.
In bidirectional reset mode (enabled by setting bit
BDRSTEN in register SYSCON) the RSTIN line is
internally pulled low for the duration of the internal
reset sequence upon any reset (HW, SW, WDT).
See note below this table.
Note: To let the reset configuration of PORT0 settle
Internal Reset Indication Output. This pin is set to a low
level when the part is executing either a hardware-, a
software- or a watchdog timer reset. RSTOUT remains
low until the EINIT (end of initialization) instruction is
executed.
Non-Maskable Interrupt Input. A high to low transition
at this pin causes the CPU to vector to the NMI trap
routine. When the PWRDN (power down) instruction is
executed, the NMI pin must be low in order to force the
C161PI to go into power down mode. If NMI is high,
when PWRDN is executed, the part will continue to run
in normal mode.
If not used, pin NMI should be pulled high externally.
and to let the PLL lock a reset duration of ca.
1 ms is recommended.
10
SS
.
&3,
1999-07