LH79520N0Q000B1 NXP Semiconductors, LH79520N0Q000B1 Datasheet - Page 18

• Manufacturer Part Number: LH79520N0Q000B1
• Description: Microcontrollers (MCU) LCD EXT BUS 3 UART MMU LQFP176
• Manufacturer: NXP Semiconductors

Specifications of LH79520N0Q000B1

• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: IrDA, SPI, SSI, UART
• Maximum Clock Frequency: 77.4144 MHz
• Number Of Programmable I/os: 64
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP
• Minimum Operating Temperature: - 40 C
• Lead Free Status / Rohs Status: Details
• Other names: LH79520N0Q000B1;55

LH79520
• Simultaneous servicing of up to 4 data streams
• Three transfer modes are supported:
• Identical source and destination capabilities
• Transfer Size Programmable (Byte, Half-word, Word)
• Burst Size Programmable
• Address Increment or Address Freeze
• Transfer Error indication for each stream via an
• 16-word FIFO array with pack and unpack logic
transfers from input to output.
Color LCD Controller (CLCDC)
drive signals to interface directly with a variety of color
and monochrome LCD panels.
• Supports single and dual scan color and mono-
• Supports Thin Film Transistor (TFT) color displays
• Programmable resolution up to 800 × 600
• 15 gray-level mono, 3,375 color STN, and 64 k color
• 1, 2, or 4 bits-per-pixel (BPP) for monochrome STN
• 1-, 2-, 4-, or 8-BPP palettized color displays for color
• True-color non-palettized, for color STN and TFT
• Programmable timing for different display panels
• 256-entry, 16-bit palette fast-access RAM
• Frame, line and pixel clock signals
• AC bias signal for STN or data enable signal for
• Patented grayscale algorithm
• Interrupt Generation Events
• Dual 16-deep programmable 32-bit wide FIFOs for
ADVANCED LCD INTERFACE
direct connection to ultra-thin panels that do not include
a timing ASIC. It converts TFT signals from the Color
LCD controller to provide the proper signals, timing and
levels for direct connection to a panel’s Row and Col-
umn drivers for AD-TFT, HR-TFT, or any technology of
panel that allows for a connection of this type. The
18
interrupt
chrome Super Twisted Nematic (STN) displays with
4- or 8-bit interfaces
TFT support
STN and TFT
TFT panels
buffering incoming data.
– Memory to Memory
– Peripheral to Memory
– Memory to Peripheral
Handles all combinations of byte, half-word or word
The CLCDC provides all the necessary control and
– 800 × 600 (16-bit color can only be supported at
The Advanced LCD Interface peripheral allows for
≤ 65 Hz refresh rates with 800 × 600 resolution).
Rev. 01 — 16 July 2007
NXP Semiconductors
Advanced LCD Interface peripheral also provides a
bypass mode that allows the LH79520 to interface to the
built-in timing ASIC in standard TFT and STN panels.
Synchronous Serial Port (SSP)
serial communication with slave peripheral devices that
support protocols for Motorola SPI, National Semicon-
ductor MICROWIRE, or Texas Instruments Synchro-
nous Serial Interface.
• Master-only operation
• Programmable clock rate
• Separate transmit FIFO and receive FIFO buffers,
• DMA for transmit and receive
• Programmable interface protocols: Motorola SPI,
• Programmable data frame size from 4 to 16 bits
• Independent masking of transmit FIFO, receive
• Available internal loopback test mode.
Universal Asynchronous
Receiver Transmitter (UART)
• Programmable use of UART0 or IrDA SIR input/output
• Separate 16-byte transmit and receive FIFOs to
• Programmable FIFO disabling for 1-byte depth
• Programmable baud rate generator
• Independent masking of transmit FIFO, receive
• False start bit detection
• Line Break generation and detection
• Fully-programmable serial interface characteristics:
• IrDA SIR Encode/Decode block, providing:
16 bits wide, 8 locations deep
National Semiconductor MICROWIRE, or Texas
Instruments Synchronous Serial Port
FIFO and receive overrun interrupts
reduce CPU interrupts
FIFO, receive timeout and modem status interrupts
The SSP is a master-only interface for synchronous
The LH79520 incorporates three UARTs.
– 5-, 6-, 7-, or 8-bit data word length
– Even-, odd- or no-parity bit generation and detection
– 1 or 2 stop bit generation
– Programmable use of IrDA SIR or UART0
– Supports data rates up to 115.2 Kbps half-duplex
– Programmable internal clock generator, allowing
input/output
division of the Reference clock in increments of 1
to 512 for low-power mode bit durations.
Preliminary data sheet
System-on-Chip