ATTINY12-8SU Atmel, ATTINY12-8SU Datasheet - Page 86
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ATTINY12-8SU
Manufacturer Part Number
ATTINY12-8SU
Description
Microcontrollers (MCU) AVR 1K FLASH 64B EE 5V 8MHZ
Manufacturer
Atmel
Datasheet
1.ATTINY12-8SU.pdf
(94 pages)
Specifications of ATTINY12-8SU
Processor Series
ATTINY1x
Core
AVR8
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
1 KB
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
6
Number Of Timers
1
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
SOIC
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500
Minimum Operating Temperature
- 40 C
Cpu Family
ATtiny
Device Core
AVR
Device Core Size
8b
Frequency (max)
8MHz
Interface Type
SPI
# I/os (max)
6
Number Of Timers - General Purpose
1
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
4V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
8
Package Type
SOIC EIAJ
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATTINY12-8SU
Manufacturer:
ATMEL
Quantity:
5
Instruction Set Summary (Continued)
86
Mnemonics
DATA TRANSFER INSTRUCTIONS
LD
ST
MOV
LDI
IN
OUT
LPM
BIT AND BIT-TEST INSTRUCTIONS
SBI
CBI
LSL
LSR
ROL
ROR
ASR
SWAP
BSET
BCLR
BST
BLD
SEC
CLC
SEN
CLN
SEZ
CLZ
SEI
CLI
SES
CLS
SEV
CLV
SET
CLT
SEH
CLH
NOP
SLEEP
WDR
ATtiny11/12
Operands
Rd,Z
Z,Rr
Rd, Rr
Rd, K
Rd, P
P, Rr
P,b
P,b
Rd
Rd
Rd
Rd
Rd
Rd
s
s
Rr, b
Rd, b
Description
Load Register Indirect
Store Register Indirect
Move Between Registers
Load Immediate
In Port
Out Port
Load Program Memory
Set Bit in I/O Register
Clear Bit in I/O Register
Logical Shift Left
Logical Shift Right
Rotate Left Through Carry
Rotate Right Through Carry
Arithmetic Shift Right
Swap Nibbles
Flag Set
Flag Clear
Bit Store from Register to T
Bit load from T to Register
Set Carry
Clear Carry
Set Negative Flag
Clear Negative Flag
Set Zero Flag
Clear Zero Flag
Global Interrupt Enable
Global Interrupt Disable
Set Signed Test Flag
Clear Signed Test Flag
Set Twos Complement Overflow
Clear Twos Complement Overflow
Set T in SREG
Clear T in SREG
Set Half Carry Flag in SREG
Clear Half Carry Flag in SREG
No Operation
Sleep
Watch Dog Reset
Operation
Rd ← (Z)
(Z) ← Rr
Rd ← Rr
Rd ← K
Rd ← P
P ← Rr
R0 ← (Z)
I/O(P,b) ← 1
I/O(P,b) ← 0
Rd(n+1) ← Rd(n), Rd(0) ← 0
Rd(n) ← Rd(n+1), Rd(7) ← 0
Rd(0) ← C, Rd(n+1) ← Rd(n), C ← Rd(7)
Rd(7) ← C, Rd(n) ← Rd(n+1), C ← Rd(0)
Rd(n) ← Rd(n+1), n = 0..6
Rd(3..0) ← Rd(7..4), Rd(7..4) ← Rd(3..0)
SREG(s) ← 1
SREG(s) ← 0
T ← Rr(b)
Rd(b) ← T
C ← 1
C ← 0
N ← 1
N ← 0
Z ← 1
Z ← 0
I ← 1
I ← 0
S ← 1
S ← 0
V ← 1
V ← 0
T ← 1
T ← 0
H ← 1
H ← 0
(see specific descr. for Sleep function)
(see specific descr. for WDR/timer)
Flags
None
None
None
None
None
None
None
None
None
Z,C,N,V
Z,C,N,V
Z,C,N,V
Z,C,N,V
Z,C,N,V
None
SREG(s)
SREG(s)
T
None
C
C
N
N
Z
Z
I
I
S
S
V
V
T
T
H
H
None
None
None
1006F–AVR–06/07
#Clocks
2
2
1
1
1
1
3
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1