ATTINY12-8SU Atmel, ATTINY12-8SU Datasheet - Page 6

• Manufacturer Part Number: ATTINY12-8SU
• Description: Microcontrollers (MCU) AVR 1K FLASH 64B EE 5V 8MHZ
• Manufacturer: Atmel

Specifications of ATTINY12-8SU

• Processor Series: ATTINY1x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 1 KB
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 6
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500
• Minimum Operating Temperature: - 40 C
• Cpu Family: ATtiny
• Device Core: AVR
• Device Core Size: 8b
• Frequency (max): 8MHz
• Interface Type: SPI
• # I/os (max): 6
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 8
• Package Type: SOIC EIAJ
• Lead Free Status / Rohs Status: Details

Architectural
Overview
6
ATtiny11/12
The fast-access register file concept contains 32 x 8-bit general-purpose working regis-
ters with a single-clock-cycle access time. This means that during one single clock
cycle, one ALU (Arithmetic Logic Unit) operation is executed. Two operands are output
from the register file, the operation is executed, and the result is stored back in the reg-
ister file – in one clock cycle.
Two of the 32 registers can be used as a 16-bit pointer for indirect memory access. This
pointer is called the Z-pointer, and can address the register file and the Flash program
memory.
The ALU supports arithmetic and logic functions between registers or between a con-
stant and a register. Single-register operations are also executed in the ALU. Figure 2
shows the ATtiny11/12 AVR RISC microcontroller architecture. The AVR uses a Har-
vard architecture concept with separate memories and buses for program and data
memories. The program memory is accessed with a two-stage pipelining. While one
instruction is being executed, the next instruction is pre-fetched from the program mem-
ory. This concept enables instructions to be executed in every clock cycle. The program
memory is reprogrammable Flash memory.
With the relative jump and relative call instructions, the whole 512 address space is
directly accessed. All AVR instructions have a single 16-bit word format, meaning that
every program memory address contains a single 16-bit instruction.
During interrupts and subroutine calls, the return address program counter (PC) is
stored on the stack. The stack is a 3-level-deep hardware stack dedicated for subrou-
tines and interrupts.
The I/O memory space contains 64 addresses for CPU peripheral functions as control
registers, timer/counters, and other I/O functions. The memory spaces in the AVR archi-
tecture are all linear and regular memory maps.
1006F–AVR–06/07